1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv6 processor support. 12 */ 13#include <linux/init.h> 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/hwcap.h> 18#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable.h> 20 21#include "proc-macros.S" 22 23#define D_CACHE_LINE_SIZE 32 24 25#define TTB_C (1 << 0) 26#define TTB_S (1 << 1) 27#define TTB_IMP (1 << 2) 28#define TTB_RGN_NC (0 << 3) 29#define TTB_RGN_WBWA (1 << 3) 30#define TTB_RGN_WT (2 << 3) 31#define TTB_RGN_WB (3 << 3) 32 33#define TTB_FLAGS_UP TTB_RGN_WBWA 34#define PMD_FLAGS_UP PMD_SECT_WB 35#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S 36#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 37 38ENTRY(cpu_v6_proc_init) 39 mov pc, lr 40 41ENTRY(cpu_v6_proc_fin) 42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 43 bic r0, r0, #0x1000 @ ...i............ 44 bic r0, r0, #0x0006 @ .............ca. 45 mcr p15, 0, r0, c1, c0, 0 @ disable caches 46 mov pc, lr 47 48/* 49 * cpu_v6_reset(loc) 50 * 51 * Perform a soft reset of the system. Put the CPU into the 52 * same state as it would be if it had been reset, and branch 53 * to what would be the reset vector. 54 * 55 * - loc - location to jump to for soft reset 56 */ 57 .align 5 58ENTRY(cpu_v6_reset) 59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 60 bic r1, r1, #0x1 @ ...............m 61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 62 mov r1, #0 63 mcr p15, 0, r1, c7, c5, 4 @ ISB 64 mov pc, r0 65 66/* 67 * cpu_v6_do_idle() 68 * 69 * Idle the processor (eg, wait for interrupt). 70 * 71 * IRQs are already disabled. 72 */ 73ENTRY(cpu_v6_do_idle) 74 mov r1, #0 75 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 77 mov pc, lr 78 79ENTRY(cpu_v6_dcache_clean_area) 80#ifndef TLB_CAN_READ_FROM_L1_CACHE 811: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 82 add r0, r0, #D_CACHE_LINE_SIZE 83 subs r1, r1, #D_CACHE_LINE_SIZE 84 bhi 1b 85#endif 86 mov pc, lr 87 88/* 89 * cpu_arm926_switch_mm(pgd_phys, tsk) 90 * 91 * Set the translation table base pointer to be pgd_phys 92 * 93 * - pgd_phys - physical address of new TTB 94 * 95 * It is assumed that: 96 * - we are not using split page tables 97 */ 98ENTRY(cpu_v6_switch_mm) 99#ifdef CONFIG_MMU 100 mov r2, #0 101 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 102 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 103 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 105 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 107 mcr p15, 0, r1, c13, c0, 1 @ set context ID 108#endif 109 mov pc, lr 110 111/* 112 * cpu_v6_set_pte_ext(ptep, pte, ext) 113 * 114 * Set a level 2 translation table entry. 115 * 116 * - ptep - pointer to level 2 translation table entry 117 * (hardware version is stored at -1024 bytes) 118 * - pte - PTE value to store 119 * - ext - value for extended PTE bits 120 */ 121 armv6_mt_table cpu_v6 122 123ENTRY(cpu_v6_set_pte_ext) 124#ifdef CONFIG_MMU 125 armv6_set_pte_ext cpu_v6 126#endif 127 mov pc, lr 128 129/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ 130.globl cpu_v6_suspend_size 131.equ cpu_v6_suspend_size, 4 * 6 132#ifdef CONFIG_PM_SLEEP 133ENTRY(cpu_v6_do_suspend) 134 stmfd sp!, {r4 - r9, lr} 135 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 136 mrc p15, 0, r5, c3, c0, 0 @ Domain ID 137 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1 138 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register 139 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control 140 mrc p15, 0, r9, c1, c0, 0 @ control register 141 stmia r0, {r4 - r9} 142 ldmfd sp!, {r4- r9, pc} 143ENDPROC(cpu_v6_do_suspend) 144 145ENTRY(cpu_v6_do_resume) 146 mov ip, #0 147 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache 148 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 149 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache 150 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 151 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 152 ldmia r0, {r4 - r9} 153 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 154 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 155 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 156 ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 157 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0 158 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1 159 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register 160 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control 161 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 162 mcr p15, 0, ip, c7, c5, 4 @ ISB 163 mov r0, r9 @ control register 164 b cpu_resume_mmu 165ENDPROC(cpu_v6_do_resume) 166#endif 167 168 string cpu_v6_name, "ARMv6-compatible processor" 169 170 .align 171 172 __CPUINIT 173 174/* 175 * __v6_setup 176 * 177 * Initialise TLB, Caches, and MMU state ready to switch the MMU 178 * on. Return in r0 the new CP15 C1 control register setting. 179 * 180 * We automatically detect if we have a Harvard cache, and use the 181 * Harvard cache control instructions insead of the unified cache 182 * control instructions. 183 * 184 * This should be able to cover all ARMv6 cores. 185 * 186 * It is assumed that: 187 * - cache type register is implemented 188 */ 189__v6_setup: 190#ifdef CONFIG_SMP 191 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode 192 ALT_UP(nop) 193 orr r0, r0, #0x20 194 ALT_SMP(mcr p15, 0, r0, c1, c0, 1) 195 ALT_UP(nop) 196#endif 197 198 mov r0, #0 199 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 200 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 201 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 202 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 203#ifdef CONFIG_MMU 204 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 205 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 206 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 207 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 208 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 209 ALT_UP(orr r8, r8, #TTB_FLAGS_UP) 210 mcr p15, 0, r8, c2, c0, 1 @ load TTB1 211#endif /* CONFIG_MMU */ 212 adr r5, v6_crval 213 ldmia r5, {r5, r6} 214#ifdef CONFIG_CPU_ENDIAN_BE8 215 orr r6, r6, #1 << 25 @ big-endian page tables 216#endif 217 mrc p15, 0, r0, c1, c0, 0 @ read control register 218 bic r0, r0, r5 @ clear bits them 219 orr r0, r0, r6 @ set them 220#ifdef CONFIG_ARM_ERRATA_364296 221 /* 222 * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data 223 * corruption with hit-under-miss enabled). The conditional code below 224 * (setting the undocumented bit 31 in the auxiliary control register 225 * and the FI bit in the control register) disables hit-under-miss 226 * without putting the processor into full low interrupt latency mode. 227 */ 228 ldr r6, =0x4107b362 @ id for ARM1136 r0p2 229 mrc p15, 0, r5, c0, c0, 0 @ get processor id 230 teq r5, r6 @ check for the faulty core 231 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg 232 orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 233 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg 234 orreq r0, r0, #(1 << 21) @ low interrupt latency configuration 235#endif 236 mov pc, lr @ return to head.S:__ret 237 238 /* 239 * V X F I D LR 240 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM 241 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 242 * 0 110 0011 1.00 .111 1101 < we want 243 */ 244 .type v6_crval, #object 245v6_crval: 246 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c 247 248 __INITDATA 249 250 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 251 define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1 252 253 .section ".rodata" 254 255 string cpu_arch_name, "armv6" 256 string cpu_elf_name, "v6" 257 .align 258 259 .section ".proc.info.init", #alloc, #execinstr 260 261 /* 262 * Match any ARMv6 processor core. 263 */ 264 .type __v6_proc_info, #object 265__v6_proc_info: 266 .long 0x0007b000 267 .long 0x0007f000 268 ALT_SMP(.long \ 269 PMD_TYPE_SECT | \ 270 PMD_SECT_AP_WRITE | \ 271 PMD_SECT_AP_READ | \ 272 PMD_FLAGS_SMP) 273 ALT_UP(.long \ 274 PMD_TYPE_SECT | \ 275 PMD_SECT_AP_WRITE | \ 276 PMD_SECT_AP_READ | \ 277 PMD_FLAGS_UP) 278 .long PMD_TYPE_SECT | \ 279 PMD_SECT_XN | \ 280 PMD_SECT_AP_WRITE | \ 281 PMD_SECT_AP_READ 282 b __v6_setup 283 .long cpu_arch_name 284 .long cpu_elf_name 285 /* See also feat_v6_fixup() for HWCAP_TLS */ 286 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS 287 .long cpu_v6_name 288 .long v6_processor_functions 289 .long v6wbi_tlb_fns 290 .long v6_user_fns 291 .long v6_cache_fns 292 .size __v6_proc_info, . - __v6_proc_info 293