1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This is the "shell" of the ARMv6 processor support. 11 */ 12#include <linux/linkage.h> 13#include <asm/assembler.h> 14#include <asm/asm-offsets.h> 15#include <asm/procinfo.h> 16#include <asm/pgtable.h> 17 18#include "proc-macros.S" 19 20#define D_CACHE_LINE_SIZE 32 21 22 .macro cpsie, flags 23 .ifc \flags, f 24 .long 0xf1080040 25 .exitm 26 .endif 27 .ifc \flags, i 28 .long 0xf1080080 29 .exitm 30 .endif 31 .ifc \flags, if 32 .long 0xf10800c0 33 .exitm 34 .endif 35 .err 36 .endm 37 38 .macro cpsid, flags 39 .ifc \flags, f 40 .long 0xf10c0040 41 .exitm 42 .endif 43 .ifc \flags, i 44 .long 0xf10c0080 45 .exitm 46 .endif 47 .ifc \flags, if 48 .long 0xf10c00c0 49 .exitm 50 .endif 51 .err 52 .endm 53 54ENTRY(cpu_v6_proc_init) 55 mov pc, lr 56 57ENTRY(cpu_v6_proc_fin) 58 stmfd sp!, {lr} 59 cpsid if @ disable interrupts 60 bl v6_flush_kern_cache_all 61 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 62 bic r0, r0, #0x1000 @ ...i............ 63 bic r0, r0, #0x0006 @ .............ca. 64 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 ldmfd sp!, {pc} 66 67/* 68 * cpu_v6_reset(loc) 69 * 70 * Perform a soft reset of the system. Put the CPU into the 71 * same state as it would be if it had been reset, and branch 72 * to what would be the reset vector. 73 * 74 * - loc - location to jump to for soft reset 75 * 76 * It is assumed that: 77 */ 78 .align 5 79ENTRY(cpu_v6_reset) 80 mov pc, r0 81 82/* 83 * cpu_v6_do_idle() 84 * 85 * Idle the processor (eg, wait for interrupt). 86 * 87 * IRQs are already disabled. 88 */ 89ENTRY(cpu_v6_do_idle) 90 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 91 mov pc, lr 92 93ENTRY(cpu_v6_dcache_clean_area) 94#ifndef TLB_CAN_READ_FROM_L1_CACHE 951: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 96 add r0, r0, #D_CACHE_LINE_SIZE 97 subs r1, r1, #D_CACHE_LINE_SIZE 98 bhi 1b 99#endif 100 mov pc, lr 101 102/* 103 * cpu_arm926_switch_mm(pgd_phys, tsk) 104 * 105 * Set the translation table base pointer to be pgd_phys 106 * 107 * - pgd_phys - physical address of new TTB 108 * 109 * It is assumed that: 110 * - we are not using split page tables 111 */ 112ENTRY(cpu_v6_switch_mm) 113 mov r2, #0 114 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 115 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 116 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 117 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 118 mcr p15, 0, r1, c13, c0, 1 @ set context ID 119 mov pc, lr 120 121/* 122 * cpu_v6_set_pte(ptep, pte) 123 * 124 * Set a level 2 translation table entry. 125 * 126 * - ptep - pointer to level 2 translation table entry 127 * (hardware version is stored at -1024 bytes) 128 * - pte - PTE value to store 129 * 130 * Permissions: 131 * YUWD APX AP1 AP0 SVC User 132 * 0xxx 0 0 0 no acc no acc 133 * 100x 1 0 1 r/o no acc 134 * 10x0 1 0 1 r/o no acc 135 * 1011 0 0 1 r/w no acc 136 * 110x 0 1 0 r/w r/o 137 * 11x0 0 1 0 r/w r/o 138 * 1111 0 1 1 r/w r/w 139 */ 140ENTRY(cpu_v6_set_pte) 141 str r1, [r0], #-2048 @ linux version 142 143 bic r2, r1, #0x000007f0 144 bic r2, r2, #0x00000003 145 orr r2, r2, #PTE_EXT_AP0 | 2 146 147 tst r1, #L_PTE_WRITE 148 tstne r1, #L_PTE_DIRTY 149 orreq r2, r2, #PTE_EXT_APX 150 151 tst r1, #L_PTE_USER 152 orrne r2, r2, #PTE_EXT_AP1 153 tstne r2, #PTE_EXT_APX 154 bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0 155 156 tst r1, #L_PTE_YOUNG 157 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK 158 159@ tst r1, #L_PTE_EXEC 160@ orreq r2, r2, #PTE_EXT_XN 161 162 tst r1, #L_PTE_PRESENT 163 moveq r2, #0 164 165 str r2, [r0] 166 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 167 mov pc, lr 168 169 170 171 172cpu_v6_name: 173 .asciz "Some Random V6 Processor" 174 .align 175 176 .section ".text.init", #alloc, #execinstr 177 178/* 179 * __v6_setup 180 * 181 * Initialise TLB, Caches, and MMU state ready to switch the MMU 182 * on. Return in r0 the new CP15 C1 control register setting. 183 * 184 * We automatically detect if we have a Harvard cache, and use the 185 * Harvard cache control instructions insead of the unified cache 186 * control instructions. 187 * 188 * This should be able to cover all ARMv6 cores. 189 * 190 * It is assumed that: 191 * - cache type register is implemented 192 */ 193__v6_setup: 194 mov r0, #0 195 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 196 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 197 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 198 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 199 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 200 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 201 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 202#ifdef CONFIG_VFP 203 mrc p15, 0, r0, c1, c0, 2 204 orr r0, r0, #(0xf << 20) 205 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP 206#endif 207 mrc p15, 0, r0, c1, c0, 0 @ read control register 208 ldr r5, v6_cr1_clear @ get mask for bits to clear 209 bic r0, r0, r5 @ clear bits them 210 ldr r5, v6_cr1_set @ get mask for bits to set 211 orr r0, r0, r5 @ set them 212 mov pc, lr @ return to head.S:__ret 213 214 /* 215 * V X F I D LR 216 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM 217 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 218 * 0 110 0011 1.00 .111 1101 < we want 219 */ 220 .type v6_cr1_clear, #object 221 .type v6_cr1_set, #object 222v6_cr1_clear: 223 .word 0x01e0fb7f 224v6_cr1_set: 225 .word 0x00c0387d 226 227 .type v6_processor_functions, #object 228ENTRY(v6_processor_functions) 229 .word v6_early_abort 230 .word cpu_v6_proc_init 231 .word cpu_v6_proc_fin 232 .word cpu_v6_reset 233 .word cpu_v6_do_idle 234 .word cpu_v6_dcache_clean_area 235 .word cpu_v6_switch_mm 236 .word cpu_v6_set_pte 237 .size v6_processor_functions, . - v6_processor_functions 238 239 .type cpu_arch_name, #object 240cpu_arch_name: 241 .asciz "armv6" 242 .size cpu_arch_name, . - cpu_arch_name 243 244 .type cpu_elf_name, #object 245cpu_elf_name: 246 .asciz "v6" 247 .size cpu_elf_name, . - cpu_elf_name 248 .align 249 250 .section ".proc.info.init", #alloc, #execinstr 251 252 /* 253 * Match any ARMv6 processor core. 254 */ 255 .type __v6_proc_info, #object 256__v6_proc_info: 257 .long 0x0007b000 258 .long 0x0007f000 259 .long PMD_TYPE_SECT | \ 260 PMD_SECT_BUFFERABLE | \ 261 PMD_SECT_CACHEABLE | \ 262 PMD_SECT_AP_WRITE | \ 263 PMD_SECT_AP_READ 264 b __v6_setup 265 .long cpu_arch_name 266 .long cpu_elf_name 267 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA 268 .long cpu_v6_name 269 .long v6_processor_functions 270 .long v6wbi_tlb_fns 271 .long v6_user_fns 272 .long v6_cache_fns 273 .size __v6_proc_info, . - __v6_proc_info 274