xref: /linux/arch/arm/mm/proc-v6.S (revision 54a8a2220c936a47840c9a3d74910c5a56fae2ed) 
1/*
2 *  linux/arch/arm/mm/proc-v6.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv6 processor support.
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/procinfo.h>
16#include <asm/pgtable.h>
17
18#include "proc-macros.S"
19
20#define D_CACHE_LINE_SIZE	32
21
22	.macro	cpsie, flags
23	.ifc \flags, f
24	.long	0xf1080040
25	.exitm
26	.endif
27	.ifc \flags, i
28	.long	0xf1080080
29	.exitm
30	.endif
31	.ifc \flags, if
32	.long	0xf10800c0
33	.exitm
34	.endif
35	.err
36	.endm
37
38	.macro	cpsid, flags
39	.ifc \flags, f
40	.long	0xf10c0040
41	.exitm
42	.endif
43	.ifc \flags, i
44	.long	0xf10c0080
45	.exitm
46	.endif
47	.ifc \flags, if
48	.long	0xf10c00c0
49	.exitm
50	.endif
51	.err
52	.endm
53
54ENTRY(cpu_v6_proc_init)
55	mov	pc, lr
56
57ENTRY(cpu_v6_proc_fin)
58	mov	pc, lr
59
60/*
61 *	cpu_v6_reset(loc)
62 *
63 *	Perform a soft reset of the system.  Put the CPU into the
64 *	same state as it would be if it had been reset, and branch
65 *	to what would be the reset vector.
66 *
67 *	- loc   - location to jump to for soft reset
68 *
69 *	It is assumed that:
70 */
71	.align	5
72ENTRY(cpu_v6_reset)
73	mov	pc, r0
74
75/*
76 *	cpu_v6_do_idle()
77 *
78 *	Idle the processor (eg, wait for interrupt).
79 *
80 *	IRQs are already disabled.
81 */
82ENTRY(cpu_v6_do_idle)
83	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
84	mov	pc, lr
85
86ENTRY(cpu_v6_dcache_clean_area)
87#ifndef TLB_CAN_READ_FROM_L1_CACHE
881:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
89	add	r0, r0, #D_CACHE_LINE_SIZE
90	subs	r1, r1, #D_CACHE_LINE_SIZE
91	bhi	1b
92#endif
93	mov	pc, lr
94
95/*
96 *	cpu_arm926_switch_mm(pgd_phys, tsk)
97 *
98 *	Set the translation table base pointer to be pgd_phys
99 *
100 *	- pgd_phys - physical address of new TTB
101 *
102 *	It is assumed that:
103 *	- we are not using split page tables
104 */
105ENTRY(cpu_v6_switch_mm)
106	mov	r2, #0
107	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
108	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
109	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
110	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
111	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
112	mov	pc, lr
113
114/*
115 *	cpu_v6_set_pte(ptep, pte)
116 *
117 *	Set a level 2 translation table entry.
118 *
119 *	- ptep  - pointer to level 2 translation table entry
120 *		  (hardware version is stored at -1024 bytes)
121 *	- pte   - PTE value to store
122 *
123 *	Permissions:
124 *	  YUWD  APX AP1 AP0	SVC	User
125 *	  0xxx   0   0   0	no acc	no acc
126 *	  100x   1   0   1	r/o	no acc
127 *	  10x0   1   0   1	r/o	no acc
128 *	  1011   0   0   1	r/w	no acc
129 *	  110x   0   1   0	r/w	r/o
130 *	  11x0   0   1   0	r/w	r/o
131 *	  1111   0   1   1	r/w	r/w
132 */
133ENTRY(cpu_v6_set_pte)
134	str	r1, [r0], #-2048		@ linux version
135
136	bic	r2, r1, #0x000007f0
137	bic	r2, r2, #0x00000003
138	orr	r2, r2, #PTE_EXT_AP0 | 2
139
140	tst	r1, #L_PTE_WRITE
141	tstne	r1, #L_PTE_DIRTY
142	orreq	r2, r2, #PTE_EXT_APX
143
144	tst	r1, #L_PTE_USER
145	orrne	r2, r2, #PTE_EXT_AP1
146	tstne	r2, #PTE_EXT_APX
147	bicne	r2, r2, #PTE_EXT_APX | PTE_EXT_AP0
148
149	tst	r1, #L_PTE_YOUNG
150	biceq	r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
151
152@	tst	r1, #L_PTE_EXEC
153@	orreq	r2, r2, #PTE_EXT_XN
154
155	tst	r1, #L_PTE_PRESENT
156	moveq	r2, #0
157
158	str	r2, [r0]
159	mcr	p15, 0, r0, c7, c10, 1 @ flush_pte
160	mov	pc, lr
161
162
163
164
165cpu_v6_name:
166	.asciz	"Some Random V6 Processor"
167	.align
168
169	.section ".text.init", #alloc, #execinstr
170
171/*
172 *	__v6_setup
173 *
174 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
175 *	on.  Return in r0 the new CP15 C1 control register setting.
176 *
177 *	We automatically detect if we have a Harvard cache, and use the
178 *	Harvard cache control instructions insead of the unified cache
179 *	control instructions.
180 *
181 *	This should be able to cover all ARMv6 cores.
182 *
183 *	It is assumed that:
184 *	- cache type register is implemented
185 */
186__v6_setup:
187	mov	r0, #0
188	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
189	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
190	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
191	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
192	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
193	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
194	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
195#ifdef CONFIG_VFP
196	mrc	p15, 0, r0, c1, c0, 2
197	orr	r0, r0, #(0xf << 20)
198	mcr	p15, 0, r0, c1, c0, 2		@ Enable full access to VFP
199#endif
200	mrc	p15, 0, r0, c1, c0, 0		@ read control register
201	ldr	r5, v6_cr1_clear		@ get mask for bits to clear
202	bic	r0, r0, r5			@ clear bits them
203	ldr	r5, v6_cr1_set			@ get mask for bits to set
204	orr	r0, r0, r5			@ set them
205	mov	pc, lr				@ return to head.S:__ret
206
207	/*
208	 *         V X F   I D LR
209	 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
210	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
211	 *         0 110       0011 1.00 .111 1101 < we want
212	 */
213	.type	v6_cr1_clear, #object
214	.type	v6_cr1_set, #object
215v6_cr1_clear:
216	.word	0x01e0fb7f
217v6_cr1_set:
218	.word	0x00c0387d
219
220	.type	v6_processor_functions, #object
221ENTRY(v6_processor_functions)
222	.word	v6_early_abort
223	.word	cpu_v6_proc_init
224	.word	cpu_v6_proc_fin
225	.word	cpu_v6_reset
226	.word	cpu_v6_do_idle
227	.word	cpu_v6_dcache_clean_area
228	.word	cpu_v6_switch_mm
229	.word	cpu_v6_set_pte
230	.size	v6_processor_functions, . - v6_processor_functions
231
232	.type	cpu_arch_name, #object
233cpu_arch_name:
234	.asciz	"armv6"
235	.size	cpu_arch_name, . - cpu_arch_name
236
237	.type	cpu_elf_name, #object
238cpu_elf_name:
239	.asciz	"v6"
240	.size	cpu_elf_name, . - cpu_elf_name
241	.align
242
243	.section ".proc.info.init", #alloc, #execinstr
244
245	/*
246	 * Match any ARMv6 processor core.
247	 */
248	.type	__v6_proc_info, #object
249__v6_proc_info:
250	.long	0x0007b000
251	.long	0x0007f000
252	.long   PMD_TYPE_SECT | \
253		PMD_SECT_BUFFERABLE | \
254		PMD_SECT_CACHEABLE | \
255		PMD_SECT_AP_WRITE | \
256		PMD_SECT_AP_READ
257	b	__v6_setup
258	.long	cpu_arch_name
259	.long	cpu_elf_name
260	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA
261	.long	cpu_v6_name
262	.long	v6_processor_functions
263	.long	v6wbi_tlb_fns
264	.long	v6_user_fns
265	.long	v6_cache_fns
266	.size	__v6_proc_info, . - __v6_proc_info
267