1/* 2 * linux/arch/arm/mm/proc-sa1100.S 3 * 4 * Copyright (C) 1997-2002 Russell King 5 * hacked for non-paged-MM by Hyok S. Choi, 2003. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * MMU functions for SA110 12 * 13 * These are the low level assembler for performing cache and TLB 14 * functions on the StrongARM-1100 and StrongARM-1110. 15 * 16 * Note that SA1100 and SA1110 share everything but their name and CPU ID. 17 * 18 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl): 19 * Flush the read buffer at context switches 20 */ 21#include <linux/linkage.h> 22#include <linux/init.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <mach/hardware.h> 27#include <asm/pgtable-hwdef.h> 28#include <asm/pgtable.h> 29 30#include "proc-macros.S" 31 32/* 33 * the cache line size of the I and D cache 34 */ 35#define DCACHELINESIZE 32 36 37 .section .text 38 39/* 40 * cpu_sa1100_proc_init() 41 */ 42ENTRY(cpu_sa1100_proc_init) 43 mov r0, #0 44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 46 ret lr 47 48/* 49 * cpu_sa1100_proc_fin() 50 * 51 * Prepare the CPU for reset: 52 * - Disable interrupts 53 * - Clean and turn off caches. 54 */ 55ENTRY(cpu_sa1100_proc_fin) 56 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 57 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 58 bic r0, r0, #0x1000 @ ...i............ 59 bic r0, r0, #0x000e @ ............wca. 60 mcr p15, 0, r0, c1, c0, 0 @ disable caches 61 ret lr 62 63/* 64 * cpu_sa1100_reset(loc) 65 * 66 * Perform a soft reset of the system. Put the CPU into the 67 * same state as it would be if it had been reset, and branch 68 * to what would be the reset vector. 69 * 70 * loc: location to jump to for soft reset 71 */ 72 .align 5 73 .pushsection .idmap.text, "ax" 74ENTRY(cpu_sa1100_reset) 75 mov ip, #0 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 77 mcr p15, 0, ip, c7, c10, 4 @ drain WB 78#ifdef CONFIG_MMU 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 80#endif 81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 82 bic ip, ip, #0x000f @ ............wcam 83 bic ip, ip, #0x1100 @ ...i...s........ 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 85 ret r0 86ENDPROC(cpu_sa1100_reset) 87 .popsection 88 89/* 90 * cpu_sa1100_do_idle(type) 91 * 92 * Cause the processor to idle 93 * 94 * type: call type: 95 * 0 = slow idle 96 * 1 = fast idle 97 * 2 = switch to slow processor clock 98 * 3 = switch to fast processor clock 99 */ 100 .align 5 101ENTRY(cpu_sa1100_do_idle) 102 mov r0, r0 @ 4 nop padding 103 mov r0, r0 104 mov r0, r0 105 mov r0, r0 @ 4 nop padding 106 mov r0, r0 107 mov r0, r0 108 mov r0, #0 109 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address 110 @ --- aligned to a cache line 111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 112 ldr r1, [r1, #0] @ force switch to MCLK 113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt 114 mov r0, r0 @ safety 115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching 116 ret lr 117 118/* ================================= CACHE ================================ */ 119 120/* 121 * cpu_sa1100_dcache_clean_area(addr,sz) 122 * 123 * Clean the specified entry of any caches such that the MMU 124 * translation fetches will obtain correct data. 125 * 126 * addr: cache-unaligned virtual address 127 */ 128 .align 5 129ENTRY(cpu_sa1100_dcache_clean_area) 1301: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 131 add r0, r0, #DCACHELINESIZE 132 subs r1, r1, #DCACHELINESIZE 133 bhi 1b 134 ret lr 135 136/* =============================== PageTable ============================== */ 137 138/* 139 * cpu_sa1100_switch_mm(pgd) 140 * 141 * Set the translation base pointer to be as described by pgd. 142 * 143 * pgd: new page tables 144 */ 145 .align 5 146ENTRY(cpu_sa1100_switch_mm) 147#ifdef CONFIG_MMU 148 str lr, [sp, #-4]! 149 bl v4wb_flush_kern_cache_all @ clears IP 150 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 151 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 153 ldr pc, [sp], #4 154#else 155 ret lr 156#endif 157 158/* 159 * cpu_sa1100_set_pte_ext(ptep, pte, ext) 160 * 161 * Set a PTE and flush it out 162 */ 163 .align 5 164ENTRY(cpu_sa1100_set_pte_ext) 165#ifdef CONFIG_MMU 166 armv3_set_pte_ext wc_disable=0 167 mov r0, r0 168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 169 mcr p15, 0, r0, c7, c10, 4 @ drain WB 170#endif 171 ret lr 172 173.globl cpu_sa1100_suspend_size 174.equ cpu_sa1100_suspend_size, 4 * 3 175#ifdef CONFIG_ARM_CPU_SUSPEND 176ENTRY(cpu_sa1100_do_suspend) 177 stmfd sp!, {r4 - r6, lr} 178 mrc p15, 0, r4, c3, c0, 0 @ domain ID 179 mrc p15, 0, r5, c13, c0, 0 @ PID 180 mrc p15, 0, r6, c1, c0, 0 @ control reg 181 stmia r0, {r4 - r6} @ store cp regs 182 ldmfd sp!, {r4 - r6, pc} 183ENDPROC(cpu_sa1100_do_suspend) 184 185ENTRY(cpu_sa1100_do_resume) 186 ldmia r0, {r4 - r6} @ load cp regs 187 mov ip, #0 188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs 189 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache 190 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 191 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB 192 193 mcr p15, 0, r4, c3, c0, 0 @ domain ID 194 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr 195 mcr p15, 0, r5, c13, c0, 0 @ PID 196 mov r0, r6 @ control register 197 b cpu_resume_mmu 198ENDPROC(cpu_sa1100_do_resume) 199#endif 200 201 .type __sa1100_setup, #function 202__sa1100_setup: 203 mov r0, #0 204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 205 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 206#ifdef CONFIG_MMU 207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 208#endif 209 adr r5, sa1100_crval 210 ldmia r5, {r5, r6} 211 mrc p15, 0, r0, c1, c0 @ get control register v4 212 bic r0, r0, r5 213 orr r0, r0, r6 214 ret lr 215 .size __sa1100_setup, . - __sa1100_setup 216 217 /* 218 * R 219 * .RVI ZFRS BLDP WCAM 220 * ..11 0001 ..11 1101 221 * 222 */ 223 .type sa1100_crval, #object 224sa1100_crval: 225 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130 226 227 __INITDATA 228 229/* 230 * SA1100 and SA1110 share the same function calls 231 */ 232 233 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 234 define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1 235 236 .section ".rodata" 237 238 string cpu_arch_name, "armv4" 239 string cpu_elf_name, "v4" 240 string cpu_sa1100_name, "StrongARM-1100" 241 string cpu_sa1110_name, "StrongARM-1110" 242 243 .align 244 245 .section ".proc.info.init", #alloc 246 247.macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req 248 .type __\name\()_proc_info,#object 249__\name\()_proc_info: 250 .long \cpu_val 251 .long \cpu_mask 252 .long PMD_TYPE_SECT | \ 253 PMD_SECT_BUFFERABLE | \ 254 PMD_SECT_CACHEABLE | \ 255 PMD_SECT_AP_WRITE | \ 256 PMD_SECT_AP_READ 257 .long PMD_TYPE_SECT | \ 258 PMD_SECT_AP_WRITE | \ 259 PMD_SECT_AP_READ 260 initfn __sa1100_setup, __\name\()_proc_info 261 .long cpu_arch_name 262 .long cpu_elf_name 263 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT 264 .long \cpu_name 265 .long sa1100_processor_functions 266 .long v4wb_tlb_fns 267 .long v4_mc_user_fns 268 .long v4wb_cache_fns 269 .size __\name\()_proc_info, . - __\name\()_proc_info 270.endm 271 272 sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name 273 sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name 274