xref: /linux/arch/arm/mm/proc-fa526.S (revision 249ebf3f65f8530beb2cbfb91bff1d83ba88d23c) 
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
4 *
5 *  Written by : Luke Lee
6 *  Copyright (C) 2005 Faraday Corp.
7 *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 *
9 * These are the low level assembler for performing cache and TLB
10 * functions on the fa526.
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <linux/cfi_types.h>
15#include <linux/pgtable.h>
16#include <asm/assembler.h>
17#include <asm/hwcap.h>
18#include <asm/pgtable-hwdef.h>
19#include <asm/page.h>
20#include <asm/ptrace.h>
21
22#include "proc-macros.S"
23
24#define CACHE_DLINESIZE	16
25
26	.text
27/*
28 * cpu_fa526_proc_init()
29 */
30SYM_TYPED_FUNC_START(cpu_fa526_proc_init)
31	ret	lr
32SYM_FUNC_END(cpu_fa526_proc_init)
33
34/*
35 * cpu_fa526_proc_fin()
36 */
37SYM_TYPED_FUNC_START(cpu_fa526_proc_fin)
38	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
39	bic	r0, r0, #0x1000			@ ...i............
40	bic	r0, r0, #0x000e			@ ............wca.
41	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
42	nop
43	nop
44	ret	lr
45SYM_FUNC_END(cpu_fa526_proc_fin)
46
47/*
48 * cpu_fa526_reset(loc)
49 *
50 * Perform a soft reset of the system.  Put the CPU into the
51 * same state as it would be if it had been reset, and branch
52 * to what would be the reset vector.
53 *
54 * loc: location to jump to for soft reset
55 */
56	.align	4
57	.pushsection	.idmap.text, "ax"
58SYM_TYPED_FUNC_START(cpu_fa526_reset)
59/* TODO: Use CP8 if possible... */
60	mov	ip, #0
61	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
62	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
63#ifdef CONFIG_MMU
64	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
65#endif
66	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
67	bic	ip, ip, #0x000f			@ ............wcam
68	bic	ip, ip, #0x1100			@ ...i...s........
69	bic	ip, ip, #0x0800			@ BTB off
70	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
71	nop
72	nop
73	ret	r0
74SYM_FUNC_END(cpu_fa526_reset)
75	.popsection
76
77/*
78 * cpu_fa526_do_idle()
79 */
80	.align	4
81SYM_TYPED_FUNC_START(cpu_fa526_do_idle)
82	ret	lr
83SYM_FUNC_END(cpu_fa526_do_idle)
84
85SYM_TYPED_FUNC_START(cpu_fa526_dcache_clean_area)
861:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
87	add	r0, r0, #CACHE_DLINESIZE
88	subs	r1, r1, #CACHE_DLINESIZE
89	bhi	1b
90	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
91	ret	lr
92SYM_FUNC_END(cpu_fa526_dcache_clean_area)
93
94/* =============================== PageTable ============================== */
95
96/*
97 * cpu_fa526_switch_mm(pgd)
98 *
99 * Set the translation base pointer to be as described by pgd.
100 *
101 * pgd: new page tables
102 */
103	.align	4
104SYM_TYPED_FUNC_START(cpu_fa526_switch_mm)
105#ifdef CONFIG_MMU
106	mov	ip, #0
107#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
108	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
109#else
110	mcr	p15, 0, ip, c7, c14, 0		@ clean and invalidate whole D cache
111#endif
112	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
113	mcr	p15, 0, ip, c7, c5, 6		@ invalidate BTB since mm changed
114	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
115	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
116	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
117	mcr	p15, 0, ip, c8, c7, 0		@ invalidate UTLB
118#endif
119	ret	lr
120SYM_FUNC_END(cpu_fa526_switch_mm)
121
122/*
123 * cpu_fa526_set_pte_ext(ptep, pte, ext)
124 *
125 * Set a PTE and flush it out
126 */
127	.align	4
128SYM_TYPED_FUNC_START(cpu_fa526_set_pte_ext)
129#ifdef CONFIG_MMU
130	armv3_set_pte_ext
131	mov	r0, r0
132	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
133	mov	r0, #0
134	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
135#endif
136	ret	lr
137SYM_FUNC_END(cpu_fa526_set_pte_ext)
138
139	.type	__fa526_setup, #function
140__fa526_setup:
141	/* On return of this routine, r0 must carry correct flags for CFG register */
142	mov	r0, #0
143	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
144	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
145#ifdef CONFIG_MMU
146	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
147#endif
148	mcr	p15, 0, r0, c7, c5, 5		@ invalidate IScratchpad RAM
149
150	mov	r0, #1
151	mcr	p15, 0, r0, c1, c1, 0		@ turn-on ECR
152
153	mov	r0, #0
154	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB All
155	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
156	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
157
158	mov	r0, #0x1f			@ Domains 0, 1 = manager, 2 = client
159	mcr	p15, 0, r0, c3, c0		@ load domain access register
160
161	mrc	p15, 0, r0, c1, c0		@ get control register v4
162	ldr	r5, fa526_cr1_clear
163	bic	r0, r0, r5
164	ldr	r5, fa526_cr1_set
165	orr	r0, r0, r5
166	ret	lr
167	.size	__fa526_setup, . - __fa526_setup
168
169	/*
170	 * .RVI ZFRS BLDP WCAM
171	 * ..11 1001 .111 1101
172	 *
173	 */
174	.type	fa526_cr1_clear, #object
175	.type	fa526_cr1_set, #object
176fa526_cr1_clear:
177	.word	0x3f3f
178fa526_cr1_set:
179	.word	0x397D
180
181	__INITDATA
182
183	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
184	define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
185
186	.section ".rodata"
187
188	string	cpu_arch_name, "armv4"
189	string	cpu_elf_name, "v4"
190	string	cpu_fa526_name, "FA526"
191
192	.align
193
194	.section ".proc.info.init", "a"
195
196	.type	__fa526_proc_info,#object
197__fa526_proc_info:
198	.long	0x66015261
199	.long	0xff01fff1
200	.long   PMD_TYPE_SECT | \
201		PMD_SECT_BUFFERABLE | \
202		PMD_SECT_CACHEABLE | \
203		PMD_BIT4 | \
204		PMD_SECT_AP_WRITE | \
205		PMD_SECT_AP_READ
206	.long   PMD_TYPE_SECT | \
207		PMD_BIT4 | \
208		PMD_SECT_AP_WRITE | \
209		PMD_SECT_AP_READ
210	initfn	__fa526_setup, __fa526_proc_info
211	.long	cpu_arch_name
212	.long	cpu_elf_name
213	.long	HWCAP_SWP | HWCAP_HALF
214	.long	cpu_fa526_name
215	.long	fa526_processor_functions
216	.long	fa_tlb_fns
217	.long	fa_user_fns
218	.long	fa_cache_fns
219	.size	__fa526_proc_info, . - __fa526_proc_info
220