1/* 2 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S 3 * 4 * Copyright (C) 1999-2001 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm926. 25 * 26 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/hwcap.h> 32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable.h> 34#include <asm/page.h> 35#include <asm/ptrace.h> 36#include "proc-macros.S" 37 38/* 39 * This is the maximum size of an area which will be invalidated 40 * using the single invalidate entry instructions. Anything larger 41 * than this, and we go for the whole cache. 42 * 43 * This value should be chosen such that we choose the cheapest 44 * alternative. 45 */ 46#define CACHE_DLIMIT 16384 47 48/* 49 * the cache line size of the I and D cache 50 */ 51#define CACHE_DLINESIZE 32 52 53 .text 54/* 55 * cpu_arm926_proc_init() 56 */ 57ENTRY(cpu_arm926_proc_init) 58 mov pc, lr 59 60/* 61 * cpu_arm926_proc_fin() 62 */ 63ENTRY(cpu_arm926_proc_fin) 64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 65 bic r0, r0, #0x1000 @ ...i............ 66 bic r0, r0, #0x000e @ ............wca. 67 mcr p15, 0, r0, c1, c0, 0 @ disable caches 68 mov pc, lr 69 70/* 71 * cpu_arm926_reset(loc) 72 * 73 * Perform a soft reset of the system. Put the CPU into the 74 * same state as it would be if it had been reset, and branch 75 * to what would be the reset vector. 76 * 77 * loc: location to jump to for soft reset 78 */ 79 .align 5 80ENTRY(cpu_arm926_reset) 81 mov ip, #0 82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 83 mcr p15, 0, ip, c7, c10, 4 @ drain WB 84#ifdef CONFIG_MMU 85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 86#endif 87 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 88 bic ip, ip, #0x000f @ ............wcam 89 bic ip, ip, #0x1100 @ ...i...s........ 90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 91 mov pc, r0 92 93/* 94 * cpu_arm926_do_idle() 95 * 96 * Called with IRQs disabled 97 */ 98 .align 10 99ENTRY(cpu_arm926_do_idle) 100 mov r0, #0 101 mrc p15, 0, r1, c1, c0, 0 @ Read control register 102 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 103 bic r2, r1, #1 << 12 104 mrs r3, cpsr @ Disable FIQs while Icache 105 orr ip, r3, #PSR_F_BIT @ is disabled 106 msr cpsr_c, ip 107 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 109 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 110 msr cpsr_c, r3 @ Restore FIQ state 111 mov pc, lr 112 113/* 114 * flush_user_cache_all() 115 * 116 * Clean and invalidate all cache entries in a particular 117 * address space. 118 */ 119ENTRY(arm926_flush_user_cache_all) 120 /* FALLTHROUGH */ 121 122/* 123 * flush_kern_cache_all() 124 * 125 * Clean and invalidate the entire cache. 126 */ 127ENTRY(arm926_flush_kern_cache_all) 128 mov r2, #VM_EXEC 129 mov ip, #0 130__flush_whole_cache: 131#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 133#else 1341: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 135 bne 1b 136#endif 137 tst r2, #VM_EXEC 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 140 mov pc, lr 141 142/* 143 * flush_user_cache_range(start, end, flags) 144 * 145 * Clean and invalidate a range of cache entries in the 146 * specified address range. 147 * 148 * - start - start address (inclusive) 149 * - end - end address (exclusive) 150 * - flags - vm_flags describing address space 151 */ 152ENTRY(arm926_flush_user_cache_range) 153 mov ip, #0 154 sub r3, r1, r0 @ calculate total size 155 cmp r3, #CACHE_DLIMIT 156 bgt __flush_whole_cache 1571: tst r2, #VM_EXEC 158#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 161 add r0, r0, #CACHE_DLINESIZE 162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 164 add r0, r0, #CACHE_DLINESIZE 165#else 166 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 168 add r0, r0, #CACHE_DLINESIZE 169 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 171 add r0, r0, #CACHE_DLINESIZE 172#endif 173 cmp r0, r1 174 blo 1b 175 tst r2, #VM_EXEC 176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 177 mov pc, lr 178 179/* 180 * coherent_kern_range(start, end) 181 * 182 * Ensure coherency between the Icache and the Dcache in the 183 * region described by start, end. If you have non-snooping 184 * Harvard caches, you need to implement this function. 185 * 186 * - start - virtual start address 187 * - end - virtual end address 188 */ 189ENTRY(arm926_coherent_kern_range) 190 /* FALLTHROUGH */ 191 192/* 193 * coherent_user_range(start, end) 194 * 195 * Ensure coherency between the Icache and the Dcache in the 196 * region described by start, end. If you have non-snooping 197 * Harvard caches, you need to implement this function. 198 * 199 * - start - virtual start address 200 * - end - virtual end address 201 */ 202ENTRY(arm926_coherent_user_range) 203 bic r0, r0, #CACHE_DLINESIZE - 1 2041: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 206 add r0, r0, #CACHE_DLINESIZE 207 cmp r0, r1 208 blo 1b 209 mcr p15, 0, r0, c7, c10, 4 @ drain WB 210 mov pc, lr 211 212/* 213 * flush_kern_dcache_area(void *addr, size_t size) 214 * 215 * Ensure no D cache aliasing occurs, either with itself or 216 * the I cache 217 * 218 * - addr - kernel address 219 * - size - region size 220 */ 221ENTRY(arm926_flush_kern_dcache_area) 222 add r1, r0, r1 2231: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 224 add r0, r0, #CACHE_DLINESIZE 225 cmp r0, r1 226 blo 1b 227 mov r0, #0 228 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 229 mcr p15, 0, r0, c7, c10, 4 @ drain WB 230 mov pc, lr 231 232/* 233 * dma_inv_range(start, end) 234 * 235 * Invalidate (discard) the specified virtual address range. 236 * May not write back any entries. If 'start' or 'end' 237 * are not cache line aligned, those lines must be written 238 * back. 239 * 240 * - start - virtual start address 241 * - end - virtual end address 242 * 243 * (same as v4wb) 244 */ 245arm926_dma_inv_range: 246#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 247 tst r0, #CACHE_DLINESIZE - 1 248 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 249 tst r1, #CACHE_DLINESIZE - 1 250 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 251#endif 252 bic r0, r0, #CACHE_DLINESIZE - 1 2531: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 254 add r0, r0, #CACHE_DLINESIZE 255 cmp r0, r1 256 blo 1b 257 mcr p15, 0, r0, c7, c10, 4 @ drain WB 258 mov pc, lr 259 260/* 261 * dma_clean_range(start, end) 262 * 263 * Clean the specified virtual address range. 264 * 265 * - start - virtual start address 266 * - end - virtual end address 267 * 268 * (same as v4wb) 269 */ 270arm926_dma_clean_range: 271#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 272 bic r0, r0, #CACHE_DLINESIZE - 1 2731: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 274 add r0, r0, #CACHE_DLINESIZE 275 cmp r0, r1 276 blo 1b 277#endif 278 mcr p15, 0, r0, c7, c10, 4 @ drain WB 279 mov pc, lr 280 281/* 282 * dma_flush_range(start, end) 283 * 284 * Clean and invalidate the specified virtual address range. 285 * 286 * - start - virtual start address 287 * - end - virtual end address 288 */ 289ENTRY(arm926_dma_flush_range) 290 bic r0, r0, #CACHE_DLINESIZE - 1 2911: 292#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 293 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 294#else 295 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 296#endif 297 add r0, r0, #CACHE_DLINESIZE 298 cmp r0, r1 299 blo 1b 300 mcr p15, 0, r0, c7, c10, 4 @ drain WB 301 mov pc, lr 302 303/* 304 * dma_map_area(start, size, dir) 305 * - start - kernel virtual start address 306 * - size - size of region 307 * - dir - DMA direction 308 */ 309ENTRY(arm926_dma_map_area) 310 add r1, r1, r0 311 cmp r2, #DMA_TO_DEVICE 312 beq arm926_dma_clean_range 313 bcs arm926_dma_inv_range 314 b arm926_dma_flush_range 315ENDPROC(arm926_dma_map_area) 316 317/* 318 * dma_unmap_area(start, size, dir) 319 * - start - kernel virtual start address 320 * - size - size of region 321 * - dir - DMA direction 322 */ 323ENTRY(arm926_dma_unmap_area) 324 mov pc, lr 325ENDPROC(arm926_dma_unmap_area) 326 327ENTRY(arm926_cache_fns) 328 .long arm926_flush_kern_cache_all 329 .long arm926_flush_user_cache_all 330 .long arm926_flush_user_cache_range 331 .long arm926_coherent_kern_range 332 .long arm926_coherent_user_range 333 .long arm926_flush_kern_dcache_area 334 .long arm926_dma_map_area 335 .long arm926_dma_unmap_area 336 .long arm926_dma_flush_range 337 338ENTRY(cpu_arm926_dcache_clean_area) 339#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 3401: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 341 add r0, r0, #CACHE_DLINESIZE 342 subs r1, r1, #CACHE_DLINESIZE 343 bhi 1b 344#endif 345 mcr p15, 0, r0, c7, c10, 4 @ drain WB 346 mov pc, lr 347 348/* =============================== PageTable ============================== */ 349 350/* 351 * cpu_arm926_switch_mm(pgd) 352 * 353 * Set the translation base pointer to be as described by pgd. 354 * 355 * pgd: new page tables 356 */ 357 .align 5 358ENTRY(cpu_arm926_switch_mm) 359#ifdef CONFIG_MMU 360 mov ip, #0 361#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 362 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 363#else 364@ && 'Clean & Invalidate whole DCache' 3651: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 366 bne 1b 367#endif 368 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 369 mcr p15, 0, ip, c7, c10, 4 @ drain WB 370 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 371 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 372#endif 373 mov pc, lr 374 375/* 376 * cpu_arm926_set_pte_ext(ptep, pte, ext) 377 * 378 * Set a PTE and flush it out 379 */ 380 .align 5 381ENTRY(cpu_arm926_set_pte_ext) 382#ifdef CONFIG_MMU 383 armv3_set_pte_ext 384 mov r0, r0 385#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 386 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 387#endif 388 mcr p15, 0, r0, c7, c10, 4 @ drain WB 389#endif 390 mov pc, lr 391 392 __INIT 393 394 .type __arm926_setup, #function 395__arm926_setup: 396 mov r0, #0 397 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 398 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 399#ifdef CONFIG_MMU 400 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 401#endif 402 403 404#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 405 mov r0, #4 @ disable write-back on caches explicitly 406 mcr p15, 7, r0, c15, c0, 0 407#endif 408 409 adr r5, arm926_crval 410 ldmia r5, {r5, r6} 411 mrc p15, 0, r0, c1, c0 @ get control register v4 412 bic r0, r0, r5 413 orr r0, r0, r6 414#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 415 orr r0, r0, #0x4000 @ .1.. .... .... .... 416#endif 417 mov pc, lr 418 .size __arm926_setup, . - __arm926_setup 419 420 /* 421 * R 422 * .RVI ZFRS BLDP WCAM 423 * .011 0001 ..11 0101 424 * 425 */ 426 .type arm926_crval, #object 427arm926_crval: 428 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134 429 430 __INITDATA 431 432/* 433 * Purpose : Function pointers used to access above functions - all calls 434 * come through these 435 */ 436 .type arm926_processor_functions, #object 437arm926_processor_functions: 438 .word v5tj_early_abort 439 .word legacy_pabort 440 .word cpu_arm926_proc_init 441 .word cpu_arm926_proc_fin 442 .word cpu_arm926_reset 443 .word cpu_arm926_do_idle 444 .word cpu_arm926_dcache_clean_area 445 .word cpu_arm926_switch_mm 446 .word cpu_arm926_set_pte_ext 447 .size arm926_processor_functions, . - arm926_processor_functions 448 449 .section ".rodata" 450 451 .type cpu_arch_name, #object 452cpu_arch_name: 453 .asciz "armv5tej" 454 .size cpu_arch_name, . - cpu_arch_name 455 456 .type cpu_elf_name, #object 457cpu_elf_name: 458 .asciz "v5" 459 .size cpu_elf_name, . - cpu_elf_name 460 461 .type cpu_arm926_name, #object 462cpu_arm926_name: 463 .asciz "ARM926EJ-S" 464 .size cpu_arm926_name, . - cpu_arm926_name 465 466 .align 467 468 .section ".proc.info.init", #alloc, #execinstr 469 470 .type __arm926_proc_info,#object 471__arm926_proc_info: 472 .long 0x41069260 @ ARM926EJ-S (v5TEJ) 473 .long 0xff0ffff0 474 .long PMD_TYPE_SECT | \ 475 PMD_SECT_BUFFERABLE | \ 476 PMD_SECT_CACHEABLE | \ 477 PMD_BIT4 | \ 478 PMD_SECT_AP_WRITE | \ 479 PMD_SECT_AP_READ 480 .long PMD_TYPE_SECT | \ 481 PMD_BIT4 | \ 482 PMD_SECT_AP_WRITE | \ 483 PMD_SECT_AP_READ 484 b __arm926_setup 485 .long cpu_arch_name 486 .long cpu_elf_name 487 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA 488 .long cpu_arm926_name 489 .long arm926_processor_functions 490 .long v4wbi_tlb_fns 491 .long v4wb_user_fns 492 .long arm926_cache_fns 493 .size __arm926_proc_info, . - __arm926_proc_info 494