1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920 4 * 5 * Copyright (C) 1999,2000 ARM Limited 6 * Copyright (C) 2000 Deep Blue Solutions Ltd. 7 * hacked for non-paged-MM by Hyok S. Choi, 2003. 8 * 9 * These are the low level assembler for performing cache and TLB 10 * functions on the arm920. 11 */ 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <linux/cfi_types.h> 15#include <linux/pgtable.h> 16#include <asm/assembler.h> 17#include <asm/hwcap.h> 18#include <asm/pgtable-hwdef.h> 19#include <asm/page.h> 20#include <asm/ptrace.h> 21#include "proc-macros.S" 22 23/* 24 * The size of one data cache line. 25 */ 26#define CACHE_DLINESIZE 32 27 28/* 29 * The number of data cache segments. 30 */ 31#define CACHE_DSEGMENTS 8 32 33/* 34 * The number of lines in a cache segment. 35 */ 36#define CACHE_DENTRIES 64 37 38/* 39 * This is the size at which it becomes more efficient to 40 * clean the whole cache, rather than using the individual 41 * cache line maintenance instructions. 42 */ 43#define CACHE_DLIMIT 65536 44 45 46 .text 47/* 48 * cpu_arm920_proc_init() 49 */ 50SYM_TYPED_FUNC_START(cpu_arm920_proc_init) 51 ret lr 52SYM_FUNC_END(cpu_arm920_proc_init) 53 54/* 55 * cpu_arm920_proc_fin() 56 */ 57SYM_TYPED_FUNC_START(cpu_arm920_proc_fin) 58 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 59 bic r0, r0, #0x1000 @ ...i............ 60 bic r0, r0, #0x000e @ ............wca. 61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 ret lr 63SYM_FUNC_END(cpu_arm920_proc_fin) 64 65/* 66 * cpu_arm920_reset(loc) 67 * 68 * Perform a soft reset of the system. Put the CPU into the 69 * same state as it would be if it had been reset, and branch 70 * to what would be the reset vector. 71 * 72 * loc: location to jump to for soft reset 73 */ 74 .align 5 75 .pushsection .idmap.text, "ax" 76SYM_TYPED_FUNC_START(cpu_arm920_reset) 77 mov ip, #0 78 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 79 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80#ifdef CONFIG_MMU 81 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 82#endif 83 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 84 bic ip, ip, #0x000f @ ............wcam 85 bic ip, ip, #0x1100 @ ...i...s........ 86 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 87 ret r0 88SYM_FUNC_END(cpu_arm920_reset) 89 .popsection 90 91/* 92 * cpu_arm920_do_idle() 93 */ 94 .align 5 95SYM_TYPED_FUNC_START(cpu_arm920_do_idle) 96 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 97 ret lr 98SYM_FUNC_END(cpu_arm920_do_idle) 99 100#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 101 102/* 103 * flush_icache_all() 104 * 105 * Unconditionally clean and invalidate the entire icache. 106 */ 107SYM_TYPED_FUNC_START(arm920_flush_icache_all) 108 mov r0, #0 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 110 ret lr 111SYM_FUNC_END(arm920_flush_icache_all) 112 113/* 114 * flush_user_cache_all() 115 * 116 * Invalidate all cache entries in a particular address 117 * space. 118 */ 119SYM_FUNC_ALIAS(arm920_flush_user_cache_all, arm920_flush_kern_cache_all) 120 121/* 122 * flush_kern_cache_all() 123 * 124 * Clean and invalidate the entire cache. 125 */ 126SYM_TYPED_FUNC_START(arm920_flush_kern_cache_all) 127 mov r2, #VM_EXEC 128 mov ip, #0 129__flush_whole_cache: 130 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments 1311: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1322: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 133 subs r3, r3, #1 << 26 134 bcs 2b @ entries 63 to 0 135 subs r1, r1, #1 << 5 136 bcs 1b @ segments 7 to 0 137 tst r2, #VM_EXEC 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 140 ret lr 141SYM_FUNC_END(arm920_flush_kern_cache_all) 142 143/* 144 * flush_user_cache_range(start, end, flags) 145 * 146 * Invalidate a range of cache entries in the specified 147 * address space. 148 * 149 * - start - start address (inclusive) 150 * - end - end address (exclusive) 151 * - flags - vm_flags for address space 152 */ 153SYM_TYPED_FUNC_START(arm920_flush_user_cache_range) 154 mov ip, #0 155 sub r3, r1, r0 @ calculate total size 156 cmp r3, #CACHE_DLIMIT 157 bhs __flush_whole_cache 158 1591: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 160 tst r2, #VM_EXEC 161 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 162 add r0, r0, #CACHE_DLINESIZE 163 cmp r0, r1 164 blo 1b 165 tst r2, #VM_EXEC 166 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 167 ret lr 168SYM_FUNC_END(arm920_flush_user_cache_range) 169 170/* 171 * coherent_kern_range(start, end) 172 * 173 * Ensure coherency between the Icache and the Dcache in the 174 * region described by start, end. If you have non-snooping 175 * Harvard caches, you need to implement this function. 176 * 177 * - start - virtual start address 178 * - end - virtual end address 179 */ 180SYM_TYPED_FUNC_START(arm920_coherent_kern_range) 181#ifdef CONFIG_CFI /* Fallthrough if !CFI */ 182 b arm920_coherent_user_range 183#endif 184SYM_FUNC_END(arm920_coherent_kern_range) 185 186/* 187 * coherent_user_range(start, end) 188 * 189 * Ensure coherency between the Icache and the Dcache in the 190 * region described by start, end. If you have non-snooping 191 * Harvard caches, you need to implement this function. 192 * 193 * - start - virtual start address 194 * - end - virtual end address 195 */ 196SYM_TYPED_FUNC_START(arm920_coherent_user_range) 197 bic r0, r0, #CACHE_DLINESIZE - 1 1981: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 199 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 200 add r0, r0, #CACHE_DLINESIZE 201 cmp r0, r1 202 blo 1b 203 mcr p15, 0, r0, c7, c10, 4 @ drain WB 204 mov r0, #0 205 ret lr 206SYM_FUNC_END(arm920_coherent_user_range) 207 208/* 209 * flush_kern_dcache_area(void *addr, size_t size) 210 * 211 * Ensure no D cache aliasing occurs, either with itself or 212 * the I cache 213 * 214 * - addr - kernel address 215 * - size - region size 216 */ 217SYM_TYPED_FUNC_START(arm920_flush_kern_dcache_area) 218 add r1, r0, r1 2191: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 220 add r0, r0, #CACHE_DLINESIZE 221 cmp r0, r1 222 blo 1b 223 mov r0, #0 224 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 225 mcr p15, 0, r0, c7, c10, 4 @ drain WB 226 ret lr 227SYM_FUNC_END(arm920_flush_kern_dcache_area) 228 229/* 230 * dma_inv_range(start, end) 231 * 232 * Invalidate (discard) the specified virtual address range. 233 * May not write back any entries. If 'start' or 'end' 234 * are not cache line aligned, those lines must be written 235 * back. 236 * 237 * - start - virtual start address 238 * - end - virtual end address 239 * 240 * (same as v4wb) 241 */ 242arm920_dma_inv_range: 243 tst r0, #CACHE_DLINESIZE - 1 244 bic r0, r0, #CACHE_DLINESIZE - 1 245 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 246 tst r1, #CACHE_DLINESIZE - 1 247 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2481: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 249 add r0, r0, #CACHE_DLINESIZE 250 cmp r0, r1 251 blo 1b 252 mcr p15, 0, r0, c7, c10, 4 @ drain WB 253 ret lr 254 255/* 256 * dma_clean_range(start, end) 257 * 258 * Clean the specified virtual address range. 259 * 260 * - start - virtual start address 261 * - end - virtual end address 262 * 263 * (same as v4wb) 264 */ 265arm920_dma_clean_range: 266 bic r0, r0, #CACHE_DLINESIZE - 1 2671: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 268 add r0, r0, #CACHE_DLINESIZE 269 cmp r0, r1 270 blo 1b 271 mcr p15, 0, r0, c7, c10, 4 @ drain WB 272 ret lr 273 274/* 275 * dma_flush_range(start, end) 276 * 277 * Clean and invalidate the specified virtual address range. 278 * 279 * - start - virtual start address 280 * - end - virtual end address 281 */ 282SYM_TYPED_FUNC_START(arm920_dma_flush_range) 283 bic r0, r0, #CACHE_DLINESIZE - 1 2841: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 285 add r0, r0, #CACHE_DLINESIZE 286 cmp r0, r1 287 blo 1b 288 mcr p15, 0, r0, c7, c10, 4 @ drain WB 289 ret lr 290SYM_FUNC_END(arm920_dma_flush_range) 291 292/* 293 * dma_map_area(start, size, dir) 294 * - start - kernel virtual start address 295 * - size - size of region 296 * - dir - DMA direction 297 */ 298SYM_TYPED_FUNC_START(arm920_dma_map_area) 299 add r1, r1, r0 300 cmp r2, #DMA_TO_DEVICE 301 beq arm920_dma_clean_range 302 bcs arm920_dma_inv_range 303 b arm920_dma_flush_range 304SYM_FUNC_END(arm920_dma_map_area) 305 306/* 307 * dma_unmap_area(start, size, dir) 308 * - start - kernel virtual start address 309 * - size - size of region 310 * - dir - DMA direction 311 */ 312SYM_TYPED_FUNC_START(arm920_dma_unmap_area) 313 ret lr 314SYM_FUNC_END(arm920_dma_unmap_area) 315 316#endif /* !CONFIG_CPU_DCACHE_WRITETHROUGH */ 317 318 319SYM_TYPED_FUNC_START(cpu_arm920_dcache_clean_area) 3201: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 321 add r0, r0, #CACHE_DLINESIZE 322 subs r1, r1, #CACHE_DLINESIZE 323 bhi 1b 324 ret lr 325SYM_FUNC_END(cpu_arm920_dcache_clean_area) 326 327/* =============================== PageTable ============================== */ 328 329/* 330 * cpu_arm920_switch_mm(pgd) 331 * 332 * Set the translation base pointer to be as described by pgd. 333 * 334 * pgd: new page tables 335 */ 336 .align 5 337SYM_TYPED_FUNC_START(cpu_arm920_switch_mm) 338#ifdef CONFIG_MMU 339 mov ip, #0 340#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 341 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 342#else 343@ && 'Clean & Invalidate whole DCache' 344@ && Re-written to use Index Ops. 345@ && Uses registers r1, r3 and ip 346 347 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments 3481: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 3492: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 350 subs r3, r3, #1 << 26 351 bcs 2b @ entries 63 to 0 352 subs r1, r1, #1 << 5 353 bcs 1b @ segments 7 to 0 354#endif 355 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 356 mcr p15, 0, ip, c7, c10, 4 @ drain WB 357 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 358 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 359#endif 360 ret lr 361SYM_FUNC_END(cpu_arm920_switch_mm) 362 363/* 364 * cpu_arm920_set_pte(ptep, pte, ext) 365 * 366 * Set a PTE and flush it out 367 */ 368 .align 5 369SYM_TYPED_FUNC_START(cpu_arm920_set_pte_ext) 370#ifdef CONFIG_MMU 371 armv3_set_pte_ext 372 mov r0, r0 373 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 374 mcr p15, 0, r0, c7, c10, 4 @ drain WB 375#endif 376 ret lr 377SYM_FUNC_END(cpu_arm920_set_pte_ext) 378 379/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ 380.globl cpu_arm920_suspend_size 381.equ cpu_arm920_suspend_size, 4 * 3 382#ifdef CONFIG_ARM_CPU_SUSPEND 383SYM_TYPED_FUNC_START(cpu_arm920_do_suspend) 384 stmfd sp!, {r4 - r6, lr} 385 mrc p15, 0, r4, c13, c0, 0 @ PID 386 mrc p15, 0, r5, c3, c0, 0 @ Domain ID 387 mrc p15, 0, r6, c1, c0, 0 @ Control register 388 stmia r0, {r4 - r6} 389 ldmfd sp!, {r4 - r6, pc} 390SYM_FUNC_END(cpu_arm920_do_suspend) 391 392SYM_TYPED_FUNC_START(cpu_arm920_do_resume) 393 mov ip, #0 394 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 395 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 396 ldmia r0, {r4 - r6} 397 mcr p15, 0, r4, c13, c0, 0 @ PID 398 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 399 mcr p15, 0, r1, c2, c0, 0 @ TTB address 400 mov r0, r6 @ control register 401 b cpu_resume_mmu 402SYM_FUNC_END(cpu_arm920_do_resume) 403#endif 404 405 .type __arm920_setup, #function 406__arm920_setup: 407 mov r0, #0 408 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 409 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 410#ifdef CONFIG_MMU 411 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 412#endif 413 adr r5, arm920_crval 414 ldmia r5, {r5, r6} 415 mrc p15, 0, r0, c1, c0 @ get control register v4 416 bic r0, r0, r5 417 orr r0, r0, r6 418 ret lr 419 .size __arm920_setup, . - __arm920_setup 420 421 /* 422 * R 423 * .RVI ZFRS BLDP WCAM 424 * ..11 0001 ..11 0101 425 * 426 */ 427 .type arm920_crval, #object 428arm920_crval: 429 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130 430 431 __INITDATA 432 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 433 define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1 434 435 .section ".rodata" 436 437 string cpu_arch_name, "armv4t" 438 string cpu_elf_name, "v4" 439 string cpu_arm920_name, "ARM920T" 440 441 .align 442 443 .section ".proc.info.init", "a" 444 445 .type __arm920_proc_info,#object 446__arm920_proc_info: 447 .long 0x41009200 448 .long 0xff00fff0 449 .long PMD_TYPE_SECT | \ 450 PMD_SECT_BUFFERABLE | \ 451 PMD_SECT_CACHEABLE | \ 452 PMD_BIT4 | \ 453 PMD_SECT_AP_WRITE | \ 454 PMD_SECT_AP_READ 455 .long PMD_TYPE_SECT | \ 456 PMD_BIT4 | \ 457 PMD_SECT_AP_WRITE | \ 458 PMD_SECT_AP_READ 459 initfn __arm920_setup, __arm920_proc_info 460 .long cpu_arch_name 461 .long cpu_elf_name 462 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 463 .long cpu_arm920_name 464 .long arm920_processor_functions 465 .long v4wbi_tlb_fns 466 .long v4wb_user_fns 467#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 468 .long arm920_cache_fns 469#else 470 .long v4wt_cache_fns 471#endif 472 .size __arm920_proc_info, . - __arm920_proc_info 473