1/* 2 * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * 13 * These are the low level assembler for performing cache and TLB 14 * functions on the ARM1022E. 15 */ 16#include <linux/linkage.h> 17#include <linux/config.h> 18#include <linux/init.h> 19#include <asm/assembler.h> 20#include <asm/asm-offsets.h> 21#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable.h> 23#include <asm/procinfo.h> 24#include <asm/ptrace.h> 25 26/* 27 * This is the maximum size of an area which will be invalidated 28 * using the single invalidate entry instructions. Anything larger 29 * than this, and we go for the whole cache. 30 * 31 * This value should be chosen such that we choose the cheapest 32 * alternative. 33 */ 34#define MAX_AREA_SIZE 32768 35 36/* 37 * The size of one data cache line. 38 */ 39#define CACHE_DLINESIZE 32 40 41/* 42 * The number of data cache segments. 43 */ 44#define CACHE_DSEGMENTS 16 45 46/* 47 * The number of lines in a cache segment. 48 */ 49#define CACHE_DENTRIES 64 50 51/* 52 * This is the size at which it becomes more efficient to 53 * clean the whole cache, rather than using the individual 54 * cache line maintainence instructions. 55 */ 56#define CACHE_DLIMIT 32768 57 58 .text 59/* 60 * cpu_arm1022_proc_init() 61 */ 62ENTRY(cpu_arm1022_proc_init) 63 mov pc, lr 64 65/* 66 * cpu_arm1022_proc_fin() 67 */ 68ENTRY(cpu_arm1022_proc_fin) 69 stmfd sp!, {lr} 70 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 71 msr cpsr_c, ip 72 bl arm1022_flush_kern_cache_all 73 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 74 bic r0, r0, #0x1000 @ ...i............ 75 bic r0, r0, #0x000e @ ............wca. 76 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 ldmfd sp!, {pc} 78 79/* 80 * cpu_arm1022_reset(loc) 81 * 82 * Perform a soft reset of the system. Put the CPU into the 83 * same state as it would be if it had been reset, and branch 84 * to what would be the reset vector. 85 * 86 * loc: location to jump to for soft reset 87 */ 88 .align 5 89ENTRY(cpu_arm1022_reset) 90 mov ip, #0 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 95 bic ip, ip, #0x000f @ ............wcam 96 bic ip, ip, #0x1100 @ ...i...s........ 97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 98 mov pc, r0 99 100/* 101 * cpu_arm1022_do_idle() 102 */ 103 .align 5 104ENTRY(cpu_arm1022_do_idle) 105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 106 mov pc, lr 107 108/* ================================= CACHE ================================ */ 109 110 .align 5 111/* 112 * flush_user_cache_all() 113 * 114 * Invalidate all cache entries in a particular address 115 * space. 116 */ 117ENTRY(arm1022_flush_user_cache_all) 118 /* FALLTHROUGH */ 119/* 120 * flush_kern_cache_all() 121 * 122 * Clean and invalidate the entire cache. 123 */ 124ENTRY(arm1022_flush_kern_cache_all) 125 mov r2, #VM_EXEC 126 mov ip, #0 127__flush_whole_cache: 128#ifndef CONFIG_CPU_DCACHE_DISABLE 129 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1301: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1312: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 132 subs r3, r3, #1 << 26 133 bcs 2b @ entries 63 to 0 134 subs r1, r1, #1 << 5 135 bcs 1b @ segments 15 to 0 136#endif 137 tst r2, #VM_EXEC 138#ifndef CONFIG_CPU_ICACHE_DISABLE 139 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 140#endif 141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 142 mov pc, lr 143 144/* 145 * flush_user_cache_range(start, end, flags) 146 * 147 * Invalidate a range of cache entries in the specified 148 * address space. 149 * 150 * - start - start address (inclusive) 151 * - end - end address (exclusive) 152 * - flags - vm_flags for this space 153 */ 154ENTRY(arm1022_flush_user_cache_range) 155 mov ip, #0 156 sub r3, r1, r0 @ calculate total size 157 cmp r3, #CACHE_DLIMIT 158 bhs __flush_whole_cache 159 160#ifndef CONFIG_CPU_DCACHE_DISABLE 1611: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 162 add r0, r0, #CACHE_DLINESIZE 163 cmp r0, r1 164 blo 1b 165#endif 166 tst r2, #VM_EXEC 167#ifndef CONFIG_CPU_ICACHE_DISABLE 168 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 169#endif 170 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 171 mov pc, lr 172 173/* 174 * coherent_kern_range(start, end) 175 * 176 * Ensure coherency between the Icache and the Dcache in the 177 * region described by start. If you have non-snooping 178 * Harvard caches, you need to implement this function. 179 * 180 * - start - virtual start address 181 * - end - virtual end address 182 */ 183ENTRY(arm1022_coherent_kern_range) 184 /* FALLTHROUGH */ 185 186/* 187 * coherent_user_range(start, end) 188 * 189 * Ensure coherency between the Icache and the Dcache in the 190 * region described by start. If you have non-snooping 191 * Harvard caches, you need to implement this function. 192 * 193 * - start - virtual start address 194 * - end - virtual end address 195 */ 196ENTRY(arm1022_coherent_user_range) 197 mov ip, #0 198 bic r0, r0, #CACHE_DLINESIZE - 1 1991: 200#ifndef CONFIG_CPU_DCACHE_DISABLE 201 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 202#endif 203#ifndef CONFIG_CPU_ICACHE_DISABLE 204 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 205#endif 206 add r0, r0, #CACHE_DLINESIZE 207 cmp r0, r1 208 blo 1b 209 mcr p15, 0, ip, c7, c10, 4 @ drain WB 210 mov pc, lr 211 212/* 213 * flush_kern_dcache_page(void *page) 214 * 215 * Ensure no D cache aliasing occurs, either with itself or 216 * the I cache 217 * 218 * - page - page aligned address 219 */ 220ENTRY(arm1022_flush_kern_dcache_page) 221 mov ip, #0 222#ifndef CONFIG_CPU_DCACHE_DISABLE 223 add r1, r0, #PAGE_SZ 2241: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 225 add r0, r0, #CACHE_DLINESIZE 226 cmp r0, r1 227 blo 1b 228#endif 229 mcr p15, 0, ip, c7, c10, 4 @ drain WB 230 mov pc, lr 231 232/* 233 * dma_inv_range(start, end) 234 * 235 * Invalidate (discard) the specified virtual address range. 236 * May not write back any entries. If 'start' or 'end' 237 * are not cache line aligned, those lines must be written 238 * back. 239 * 240 * - start - virtual start address 241 * - end - virtual end address 242 * 243 * (same as v4wb) 244 */ 245ENTRY(arm1022_dma_inv_range) 246 mov ip, #0 247#ifndef CONFIG_CPU_DCACHE_DISABLE 248 tst r0, #CACHE_DLINESIZE - 1 249 bic r0, r0, #CACHE_DLINESIZE - 1 250 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 251 tst r1, #CACHE_DLINESIZE - 1 252 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2531: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 254 add r0, r0, #CACHE_DLINESIZE 255 cmp r0, r1 256 blo 1b 257#endif 258 mcr p15, 0, ip, c7, c10, 4 @ drain WB 259 mov pc, lr 260 261/* 262 * dma_clean_range(start, end) 263 * 264 * Clean the specified virtual address range. 265 * 266 * - start - virtual start address 267 * - end - virtual end address 268 * 269 * (same as v4wb) 270 */ 271ENTRY(arm1022_dma_clean_range) 272 mov ip, #0 273#ifndef CONFIG_CPU_DCACHE_DISABLE 274 bic r0, r0, #CACHE_DLINESIZE - 1 2751: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 276 add r0, r0, #CACHE_DLINESIZE 277 cmp r0, r1 278 blo 1b 279#endif 280 mcr p15, 0, ip, c7, c10, 4 @ drain WB 281 mov pc, lr 282 283/* 284 * dma_flush_range(start, end) 285 * 286 * Clean and invalidate the specified virtual address range. 287 * 288 * - start - virtual start address 289 * - end - virtual end address 290 */ 291ENTRY(arm1022_dma_flush_range) 292 mov ip, #0 293#ifndef CONFIG_CPU_DCACHE_DISABLE 294 bic r0, r0, #CACHE_DLINESIZE - 1 2951: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 296 add r0, r0, #CACHE_DLINESIZE 297 cmp r0, r1 298 blo 1b 299#endif 300 mcr p15, 0, ip, c7, c10, 4 @ drain WB 301 mov pc, lr 302 303ENTRY(arm1022_cache_fns) 304 .long arm1022_flush_kern_cache_all 305 .long arm1022_flush_user_cache_all 306 .long arm1022_flush_user_cache_range 307 .long arm1022_coherent_kern_range 308 .long arm1022_coherent_user_range 309 .long arm1022_flush_kern_dcache_page 310 .long arm1022_dma_inv_range 311 .long arm1022_dma_clean_range 312 .long arm1022_dma_flush_range 313 314 .align 5 315ENTRY(cpu_arm1022_dcache_clean_area) 316#ifndef CONFIG_CPU_DCACHE_DISABLE 317 mov ip, #0 3181: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 319 add r0, r0, #CACHE_DLINESIZE 320 subs r1, r1, #CACHE_DLINESIZE 321 bhi 1b 322#endif 323 mov pc, lr 324 325/* =============================== PageTable ============================== */ 326 327/* 328 * cpu_arm1022_switch_mm(pgd) 329 * 330 * Set the translation base pointer to be as described by pgd. 331 * 332 * pgd: new page tables 333 */ 334 .align 5 335ENTRY(cpu_arm1022_switch_mm) 336#ifndef CONFIG_CPU_DCACHE_DISABLE 337 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 3381: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 3392: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 340 subs r3, r3, #1 << 26 341 bcs 2b @ entries 63 to 0 342 subs r1, r1, #1 << 5 343 bcs 1b @ segments 15 to 0 344#endif 345 mov r1, #0 346#ifndef CONFIG_CPU_ICACHE_DISABLE 347 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 348#endif 349 mcr p15, 0, r1, c7, c10, 4 @ drain WB 350 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 351 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 352 mov pc, lr 353 354/* 355 * cpu_arm1022_set_pte(ptep, pte) 356 * 357 * Set a PTE and flush it out 358 */ 359 .align 5 360ENTRY(cpu_arm1022_set_pte) 361 str r1, [r0], #-2048 @ linux version 362 363 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 364 365 bic r2, r1, #PTE_SMALL_AP_MASK 366 bic r2, r2, #PTE_TYPE_MASK 367 orr r2, r2, #PTE_TYPE_SMALL 368 369 tst r1, #L_PTE_USER @ User? 370 orrne r2, r2, #PTE_SMALL_AP_URO_SRW 371 372 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 373 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW 374 375 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 376 movne r2, #0 377 378#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 379 eor r3, r1, #0x0a @ C & small page? 380 tst r3, #0x0b 381 biceq r2, r2, #4 382#endif 383 str r2, [r0] @ hardware version 384 mov r0, r0 385#ifndef CONFIG_CPU_DCACHE_DISABLE 386 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 387#endif 388 mov pc, lr 389 390 __INIT 391 392 .type __arm1022_setup, #function 393__arm1022_setup: 394 mov r0, #0 395 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 396 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 398 mrc p15, 0, r0, c1, c0 @ get control register v4 399 ldr r5, arm1022_cr1_clear 400 bic r0, r0, r5 401 ldr r5, arm1022_cr1_set 402 orr r0, r0, r5 403#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 404 orr r0, r0, #0x4000 @ .R.............. 405#endif 406 mov pc, lr 407 .size __arm1022_setup, . - __arm1022_setup 408 409 /* 410 * R 411 * .RVI ZFRS BLDP WCAM 412 * .011 1001 ..11 0101 413 * 414 */ 415 .type arm1022_cr1_clear, #object 416 .type arm1022_cr1_set, #object 417arm1022_cr1_clear: 418 .word 0x7f3f 419arm1022_cr1_set: 420 .word 0x3935 421 422 __INITDATA 423 424/* 425 * Purpose : Function pointers used to access above functions - all calls 426 * come through these 427 */ 428 .type arm1022_processor_functions, #object 429arm1022_processor_functions: 430 .word v4t_early_abort 431 .word cpu_arm1022_proc_init 432 .word cpu_arm1022_proc_fin 433 .word cpu_arm1022_reset 434 .word cpu_arm1022_do_idle 435 .word cpu_arm1022_dcache_clean_area 436 .word cpu_arm1022_switch_mm 437 .word cpu_arm1022_set_pte 438 .size arm1022_processor_functions, . - arm1022_processor_functions 439 440 .section ".rodata" 441 442 .type cpu_arch_name, #object 443cpu_arch_name: 444 .asciz "armv5te" 445 .size cpu_arch_name, . - cpu_arch_name 446 447 .type cpu_elf_name, #object 448cpu_elf_name: 449 .asciz "v5" 450 .size cpu_elf_name, . - cpu_elf_name 451 452 .type cpu_arm1022_name, #object 453cpu_arm1022_name: 454 .ascii "arm1022" 455#ifndef CONFIG_CPU_ICACHE_DISABLE 456 .ascii "i" 457#endif 458#ifndef CONFIG_CPU_DCACHE_DISABLE 459 .ascii "d" 460#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 461 .ascii "(wt)" 462#else 463 .ascii "(wb)" 464#endif 465#endif 466#ifndef CONFIG_CPU_BPREDICT_DISABLE 467 .ascii "B" 468#endif 469#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 470 .ascii "RR" 471#endif 472 .ascii "\0" 473 .size cpu_arm1022_name, . - cpu_arm1022_name 474 475 .align 476 477 .section ".proc.info.init", #alloc, #execinstr 478 479 .type __arm1022_proc_info,#object 480__arm1022_proc_info: 481 .long 0x4105a220 @ ARM 1022E (v5TE) 482 .long 0xff0ffff0 483 .long PMD_TYPE_SECT | \ 484 PMD_BIT4 | \ 485 PMD_SECT_AP_WRITE | \ 486 PMD_SECT_AP_READ 487 b __arm1022_setup 488 .long cpu_arch_name 489 .long cpu_elf_name 490 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP 491 .long cpu_arm1022_name 492 .long arm1022_processor_functions 493 .long v4wbi_tlb_fns 494 .long v4wb_user_fns 495 .long arm1022_cache_fns 496 .size __arm1022_proc_info, . - __arm1022_proc_info 497