1/* 2 * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * 14 * These are the low level assembler for performing cache and TLB 15 * functions on the ARM1022E. 16 */ 17#include <linux/linkage.h> 18#include <linux/init.h> 19#include <asm/assembler.h> 20#include <asm/asm-offsets.h> 21#include <asm/hwcap.h> 22#include <asm/pgtable-hwdef.h> 23#include <asm/pgtable.h> 24#include <asm/ptrace.h> 25 26#include "proc-macros.S" 27 28/* 29 * This is the maximum size of an area which will be invalidated 30 * using the single invalidate entry instructions. Anything larger 31 * than this, and we go for the whole cache. 32 * 33 * This value should be chosen such that we choose the cheapest 34 * alternative. 35 */ 36#define MAX_AREA_SIZE 32768 37 38/* 39 * The size of one data cache line. 40 */ 41#define CACHE_DLINESIZE 32 42 43/* 44 * The number of data cache segments. 45 */ 46#define CACHE_DSEGMENTS 16 47 48/* 49 * The number of lines in a cache segment. 50 */ 51#define CACHE_DENTRIES 64 52 53/* 54 * This is the size at which it becomes more efficient to 55 * clean the whole cache, rather than using the individual 56 * cache line maintainence instructions. 57 */ 58#define CACHE_DLIMIT 32768 59 60 .text 61/* 62 * cpu_arm1022_proc_init() 63 */ 64ENTRY(cpu_arm1022_proc_init) 65 mov pc, lr 66 67/* 68 * cpu_arm1022_proc_fin() 69 */ 70ENTRY(cpu_arm1022_proc_fin) 71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 72 bic r0, r0, #0x1000 @ ...i............ 73 bic r0, r0, #0x000e @ ............wca. 74 mcr p15, 0, r0, c1, c0, 0 @ disable caches 75 mov pc, lr 76 77/* 78 * cpu_arm1022_reset(loc) 79 * 80 * Perform a soft reset of the system. Put the CPU into the 81 * same state as it would be if it had been reset, and branch 82 * to what would be the reset vector. 83 * 84 * loc: location to jump to for soft reset 85 */ 86 .align 5 87ENTRY(cpu_arm1022_reset) 88 mov ip, #0 89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 90 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91#ifdef CONFIG_MMU 92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93#endif 94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 95 bic ip, ip, #0x000f @ ............wcam 96 bic ip, ip, #0x1100 @ ...i...s........ 97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 98 mov pc, r0 99 100/* 101 * cpu_arm1022_do_idle() 102 */ 103 .align 5 104ENTRY(cpu_arm1022_do_idle) 105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 106 mov pc, lr 107 108/* ================================= CACHE ================================ */ 109 110 .align 5 111/* 112 * flush_user_cache_all() 113 * 114 * Invalidate all cache entries in a particular address 115 * space. 116 */ 117ENTRY(arm1022_flush_user_cache_all) 118 /* FALLTHROUGH */ 119/* 120 * flush_kern_cache_all() 121 * 122 * Clean and invalidate the entire cache. 123 */ 124ENTRY(arm1022_flush_kern_cache_all) 125 mov r2, #VM_EXEC 126 mov ip, #0 127__flush_whole_cache: 128#ifndef CONFIG_CPU_DCACHE_DISABLE 129 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1301: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1312: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 132 subs r3, r3, #1 << 26 133 bcs 2b @ entries 63 to 0 134 subs r1, r1, #1 << 5 135 bcs 1b @ segments 15 to 0 136#endif 137 tst r2, #VM_EXEC 138#ifndef CONFIG_CPU_ICACHE_DISABLE 139 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 140#endif 141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 142 mov pc, lr 143 144/* 145 * flush_user_cache_range(start, end, flags) 146 * 147 * Invalidate a range of cache entries in the specified 148 * address space. 149 * 150 * - start - start address (inclusive) 151 * - end - end address (exclusive) 152 * - flags - vm_flags for this space 153 */ 154ENTRY(arm1022_flush_user_cache_range) 155 mov ip, #0 156 sub r3, r1, r0 @ calculate total size 157 cmp r3, #CACHE_DLIMIT 158 bhs __flush_whole_cache 159 160#ifndef CONFIG_CPU_DCACHE_DISABLE 1611: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 162 add r0, r0, #CACHE_DLINESIZE 163 cmp r0, r1 164 blo 1b 165#endif 166 tst r2, #VM_EXEC 167#ifndef CONFIG_CPU_ICACHE_DISABLE 168 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 169#endif 170 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 171 mov pc, lr 172 173/* 174 * coherent_kern_range(start, end) 175 * 176 * Ensure coherency between the Icache and the Dcache in the 177 * region described by start. If you have non-snooping 178 * Harvard caches, you need to implement this function. 179 * 180 * - start - virtual start address 181 * - end - virtual end address 182 */ 183ENTRY(arm1022_coherent_kern_range) 184 /* FALLTHROUGH */ 185 186/* 187 * coherent_user_range(start, end) 188 * 189 * Ensure coherency between the Icache and the Dcache in the 190 * region described by start. If you have non-snooping 191 * Harvard caches, you need to implement this function. 192 * 193 * - start - virtual start address 194 * - end - virtual end address 195 */ 196ENTRY(arm1022_coherent_user_range) 197 mov ip, #0 198 bic r0, r0, #CACHE_DLINESIZE - 1 1991: 200#ifndef CONFIG_CPU_DCACHE_DISABLE 201 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 202#endif 203#ifndef CONFIG_CPU_ICACHE_DISABLE 204 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 205#endif 206 add r0, r0, #CACHE_DLINESIZE 207 cmp r0, r1 208 blo 1b 209 mcr p15, 0, ip, c7, c10, 4 @ drain WB 210 mov pc, lr 211 212/* 213 * flush_kern_dcache_area(void *addr, size_t size) 214 * 215 * Ensure no D cache aliasing occurs, either with itself or 216 * the I cache 217 * 218 * - addr - kernel address 219 * - size - region size 220 */ 221ENTRY(arm1022_flush_kern_dcache_area) 222 mov ip, #0 223#ifndef CONFIG_CPU_DCACHE_DISABLE 224 add r1, r0, r1 2251: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 226 add r0, r0, #CACHE_DLINESIZE 227 cmp r0, r1 228 blo 1b 229#endif 230 mcr p15, 0, ip, c7, c10, 4 @ drain WB 231 mov pc, lr 232 233/* 234 * dma_inv_range(start, end) 235 * 236 * Invalidate (discard) the specified virtual address range. 237 * May not write back any entries. If 'start' or 'end' 238 * are not cache line aligned, those lines must be written 239 * back. 240 * 241 * - start - virtual start address 242 * - end - virtual end address 243 * 244 * (same as v4wb) 245 */ 246arm1022_dma_inv_range: 247 mov ip, #0 248#ifndef CONFIG_CPU_DCACHE_DISABLE 249 tst r0, #CACHE_DLINESIZE - 1 250 bic r0, r0, #CACHE_DLINESIZE - 1 251 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 252 tst r1, #CACHE_DLINESIZE - 1 253 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2541: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 255 add r0, r0, #CACHE_DLINESIZE 256 cmp r0, r1 257 blo 1b 258#endif 259 mcr p15, 0, ip, c7, c10, 4 @ drain WB 260 mov pc, lr 261 262/* 263 * dma_clean_range(start, end) 264 * 265 * Clean the specified virtual address range. 266 * 267 * - start - virtual start address 268 * - end - virtual end address 269 * 270 * (same as v4wb) 271 */ 272arm1022_dma_clean_range: 273 mov ip, #0 274#ifndef CONFIG_CPU_DCACHE_DISABLE 275 bic r0, r0, #CACHE_DLINESIZE - 1 2761: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 277 add r0, r0, #CACHE_DLINESIZE 278 cmp r0, r1 279 blo 1b 280#endif 281 mcr p15, 0, ip, c7, c10, 4 @ drain WB 282 mov pc, lr 283 284/* 285 * dma_flush_range(start, end) 286 * 287 * Clean and invalidate the specified virtual address range. 288 * 289 * - start - virtual start address 290 * - end - virtual end address 291 */ 292ENTRY(arm1022_dma_flush_range) 293 mov ip, #0 294#ifndef CONFIG_CPU_DCACHE_DISABLE 295 bic r0, r0, #CACHE_DLINESIZE - 1 2961: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 297 add r0, r0, #CACHE_DLINESIZE 298 cmp r0, r1 299 blo 1b 300#endif 301 mcr p15, 0, ip, c7, c10, 4 @ drain WB 302 mov pc, lr 303 304/* 305 * dma_map_area(start, size, dir) 306 * - start - kernel virtual start address 307 * - size - size of region 308 * - dir - DMA direction 309 */ 310ENTRY(arm1022_dma_map_area) 311 add r1, r1, r0 312 cmp r2, #DMA_TO_DEVICE 313 beq arm1022_dma_clean_range 314 bcs arm1022_dma_inv_range 315 b arm1022_dma_flush_range 316ENDPROC(arm1022_dma_map_area) 317 318/* 319 * dma_unmap_area(start, size, dir) 320 * - start - kernel virtual start address 321 * - size - size of region 322 * - dir - DMA direction 323 */ 324ENTRY(arm1022_dma_unmap_area) 325 mov pc, lr 326ENDPROC(arm1022_dma_unmap_area) 327 328ENTRY(arm1022_cache_fns) 329 .long arm1022_flush_kern_cache_all 330 .long arm1022_flush_user_cache_all 331 .long arm1022_flush_user_cache_range 332 .long arm1022_coherent_kern_range 333 .long arm1022_coherent_user_range 334 .long arm1022_flush_kern_dcache_area 335 .long arm1022_dma_map_area 336 .long arm1022_dma_unmap_area 337 .long arm1022_dma_flush_range 338 339 .align 5 340ENTRY(cpu_arm1022_dcache_clean_area) 341#ifndef CONFIG_CPU_DCACHE_DISABLE 342 mov ip, #0 3431: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 344 add r0, r0, #CACHE_DLINESIZE 345 subs r1, r1, #CACHE_DLINESIZE 346 bhi 1b 347#endif 348 mov pc, lr 349 350/* =============================== PageTable ============================== */ 351 352/* 353 * cpu_arm1022_switch_mm(pgd) 354 * 355 * Set the translation base pointer to be as described by pgd. 356 * 357 * pgd: new page tables 358 */ 359 .align 5 360ENTRY(cpu_arm1022_switch_mm) 361#ifdef CONFIG_MMU 362#ifndef CONFIG_CPU_DCACHE_DISABLE 363 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 3641: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 3652: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 366 subs r3, r3, #1 << 26 367 bcs 2b @ entries 63 to 0 368 subs r1, r1, #1 << 5 369 bcs 1b @ segments 15 to 0 370#endif 371 mov r1, #0 372#ifndef CONFIG_CPU_ICACHE_DISABLE 373 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 374#endif 375 mcr p15, 0, r1, c7, c10, 4 @ drain WB 376 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 377 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 378#endif 379 mov pc, lr 380 381/* 382 * cpu_arm1022_set_pte_ext(ptep, pte, ext) 383 * 384 * Set a PTE and flush it out 385 */ 386 .align 5 387ENTRY(cpu_arm1022_set_pte_ext) 388#ifdef CONFIG_MMU 389 armv3_set_pte_ext 390 mov r0, r0 391#ifndef CONFIG_CPU_DCACHE_DISABLE 392 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 393#endif 394#endif /* CONFIG_MMU */ 395 mov pc, lr 396 397 __INIT 398 399 .type __arm1022_setup, #function 400__arm1022_setup: 401 mov r0, #0 402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 403 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 404#ifdef CONFIG_MMU 405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 406#endif 407 adr r5, arm1022_crval 408 ldmia r5, {r5, r6} 409 mrc p15, 0, r0, c1, c0 @ get control register v4 410 bic r0, r0, r5 411 orr r0, r0, r6 412#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 413 orr r0, r0, #0x4000 @ .R.............. 414#endif 415 mov pc, lr 416 .size __arm1022_setup, . - __arm1022_setup 417 418 /* 419 * R 420 * .RVI ZFRS BLDP WCAM 421 * .011 1001 ..11 0101 422 * 423 */ 424 .type arm1022_crval, #object 425arm1022_crval: 426 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930 427 428 __INITDATA 429 430/* 431 * Purpose : Function pointers used to access above functions - all calls 432 * come through these 433 */ 434 .type arm1022_processor_functions, #object 435arm1022_processor_functions: 436 .word v4t_early_abort 437 .word legacy_pabort 438 .word cpu_arm1022_proc_init 439 .word cpu_arm1022_proc_fin 440 .word cpu_arm1022_reset 441 .word cpu_arm1022_do_idle 442 .word cpu_arm1022_dcache_clean_area 443 .word cpu_arm1022_switch_mm 444 .word cpu_arm1022_set_pte_ext 445 .size arm1022_processor_functions, . - arm1022_processor_functions 446 447 .section ".rodata" 448 449 .type cpu_arch_name, #object 450cpu_arch_name: 451 .asciz "armv5te" 452 .size cpu_arch_name, . - cpu_arch_name 453 454 .type cpu_elf_name, #object 455cpu_elf_name: 456 .asciz "v5" 457 .size cpu_elf_name, . - cpu_elf_name 458 459 .type cpu_arm1022_name, #object 460cpu_arm1022_name: 461 .asciz "ARM1022" 462 .size cpu_arm1022_name, . - cpu_arm1022_name 463 464 .align 465 466 .section ".proc.info.init", #alloc, #execinstr 467 468 .type __arm1022_proc_info,#object 469__arm1022_proc_info: 470 .long 0x4105a220 @ ARM 1022E (v5TE) 471 .long 0xff0ffff0 472 .long PMD_TYPE_SECT | \ 473 PMD_BIT4 | \ 474 PMD_SECT_AP_WRITE | \ 475 PMD_SECT_AP_READ 476 .long PMD_TYPE_SECT | \ 477 PMD_BIT4 | \ 478 PMD_SECT_AP_WRITE | \ 479 PMD_SECT_AP_READ 480 b __arm1022_setup 481 .long cpu_arch_name 482 .long cpu_elf_name 483 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP 484 .long cpu_arm1022_name 485 .long arm1022_processor_functions 486 .long v4wbi_tlb_fns 487 .long v4wb_user_fns 488 .long arm1022_cache_fns 489 .size __arm1022_proc_info, . - __arm1022_proc_info 490