1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mm/nommu.c 4 * 5 * ARM uCLinux supporting functions. 6 */ 7 #include <linux/module.h> 8 #include <linux/mm.h> 9 #include <linux/pagemap.h> 10 #include <linux/io.h> 11 #include <linux/memblock.h> 12 #include <linux/kernel.h> 13 14 #include <asm/cacheflush.h> 15 #include <asm/cp15.h> 16 #include <asm/sections.h> 17 #include <asm/page.h> 18 #include <asm/setup.h> 19 #include <asm/traps.h> 20 #include <asm/mach/arch.h> 21 #include <asm/cputype.h> 22 #include <asm/mpu.h> 23 #include <asm/procinfo.h> 24 #include <asm/idmap.h> 25 26 #include "mm.h" 27 28 unsigned long vectors_base; 29 30 #ifdef CONFIG_ARM_MPU 31 struct mpu_rgn_info mpu_rgn_info; 32 #endif 33 34 #ifdef CONFIG_CPU_CP15 35 #ifdef CONFIG_CPU_HIGH_VECTOR 36 unsigned long setup_vectors_base(void) 37 { 38 unsigned long reg = get_cr(); 39 40 set_cr(reg | CR_V); 41 return 0xffff0000; 42 } 43 #else /* CONFIG_CPU_HIGH_VECTOR */ 44 /* Write exception base address to VBAR */ 45 static inline void set_vbar(unsigned long val) 46 { 47 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); 48 } 49 50 /* 51 * Security extensions, bits[7:4], permitted values, 52 * 0b0000 - not implemented, 0b0001/0b0010 - implemented 53 */ 54 static inline bool security_extensions_enabled(void) 55 { 56 /* Check CPUID Identification Scheme before ID_PFR1 read */ 57 if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) 58 return cpuid_feature_extract(CPUID_EXT_PFR1, 4) || 59 cpuid_feature_extract(CPUID_EXT_PFR1, 20); 60 return 0; 61 } 62 63 unsigned long setup_vectors_base(void) 64 { 65 unsigned long base = 0, reg = get_cr(); 66 67 set_cr(reg & ~CR_V); 68 if (security_extensions_enabled()) { 69 if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) 70 base = CONFIG_DRAM_BASE; 71 set_vbar(base); 72 } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) { 73 if (CONFIG_DRAM_BASE != 0) 74 pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n"); 75 } 76 77 return base; 78 } 79 #endif /* CONFIG_CPU_HIGH_VECTOR */ 80 #endif /* CONFIG_CPU_CP15 */ 81 82 void __init arm_mm_memblock_reserve(void) 83 { 84 #ifndef CONFIG_CPU_V7M 85 vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0; 86 /* 87 * Register the exception vector page. 88 * some architectures which the DRAM is the exception vector to trap, 89 * alloc_page breaks with error, although it is not NULL, but "0." 90 */ 91 memblock_reserve(vectors_base, 2 * PAGE_SIZE); 92 #else /* ifndef CONFIG_CPU_V7M */ 93 /* 94 * There is no dedicated vector page on V7-M. So nothing needs to be 95 * reserved here. 96 */ 97 #endif 98 /* 99 * In any case, always ensure address 0 is never used as many things 100 * get very confused if 0 is returned as a legitimate address. 101 */ 102 memblock_reserve(0, 1); 103 } 104 105 static void __init adjust_lowmem_bounds_mpu(void) 106 { 107 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA; 108 109 switch (pmsa) { 110 case MMFR0_PMSAv7: 111 pmsav7_adjust_lowmem_bounds(); 112 break; 113 case MMFR0_PMSAv8: 114 pmsav8_adjust_lowmem_bounds(); 115 break; 116 default: 117 break; 118 } 119 } 120 121 static void __init mpu_setup(void) 122 { 123 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA; 124 125 switch (pmsa) { 126 case MMFR0_PMSAv7: 127 pmsav7_setup(); 128 break; 129 case MMFR0_PMSAv8: 130 pmsav8_setup(); 131 break; 132 default: 133 break; 134 } 135 } 136 137 void __init adjust_lowmem_bounds(void) 138 { 139 phys_addr_t end; 140 adjust_lowmem_bounds_mpu(); 141 end = memblock_end_of_DRAM(); 142 high_memory = __va(end - 1) + 1; 143 memblock_set_current_limit(end); 144 } 145 146 /* 147 * paging_init() sets up the page tables, initialises the zone memory 148 * maps, and sets up the zero page, bad page and bad page tables. 149 */ 150 void __init paging_init(const struct machine_desc *mdesc) 151 { 152 early_trap_init((void *)vectors_base); 153 mpu_setup(); 154 155 bootmem_init(); 156 } 157 158 /* 159 * We don't need to do anything here for nommu machines. 160 */ 161 void setup_mm_for_reboot(void) 162 { 163 } 164 165 void flush_dcache_folio(struct folio *folio) 166 { 167 __cpuc_flush_dcache_area(folio_address(folio), folio_size(folio)); 168 } 169 EXPORT_SYMBOL(flush_dcache_folio); 170 171 void flush_dcache_page(struct page *page) 172 { 173 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); 174 } 175 EXPORT_SYMBOL(flush_dcache_page); 176 177 void copy_to_user_page(struct vm_area_struct *vma, struct page *page, 178 unsigned long uaddr, void *dst, const void *src, 179 unsigned long len) 180 { 181 memcpy(dst, src, len); 182 if (vma->vm_flags & VM_EXEC) 183 __cpuc_coherent_user_range(uaddr, uaddr + len); 184 } 185 186 void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, 187 size_t size, unsigned int mtype) 188 { 189 if (pfn >= (0x100000000ULL >> PAGE_SHIFT)) 190 return NULL; 191 return (void __iomem *) (offset + (pfn << PAGE_SHIFT)); 192 } 193 EXPORT_SYMBOL(__arm_ioremap_pfn); 194 195 void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size, 196 unsigned int mtype, void *caller) 197 { 198 return (void __iomem *)phys_addr; 199 } 200 201 void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *); 202 203 void __iomem *ioremap(resource_size_t res_cookie, size_t size) 204 { 205 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE, 206 __builtin_return_address(0)); 207 } 208 EXPORT_SYMBOL(ioremap); 209 210 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size) 211 { 212 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED, 213 __builtin_return_address(0)); 214 } 215 EXPORT_SYMBOL(ioremap_cache); 216 217 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) 218 { 219 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC, 220 __builtin_return_address(0)); 221 } 222 EXPORT_SYMBOL(ioremap_wc); 223 224 #ifdef CONFIG_PCI 225 226 #include <asm/mach/map.h> 227 228 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size) 229 { 230 return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, 231 __builtin_return_address(0)); 232 } 233 EXPORT_SYMBOL_GPL(pci_remap_cfgspace); 234 #endif 235 236 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size, unsigned long flags) 237 { 238 return (void *)phys_addr; 239 } 240 241 void iounmap(volatile void __iomem *io_addr) 242 { 243 } 244 EXPORT_SYMBOL(iounmap); 245