1 /* 2 * linux/arch/arm/mm/mmu.c 3 * 4 * Copyright (C) 1995-2005 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/mman.h> 15 #include <linux/nodemask.h> 16 #include <linux/memblock.h> 17 #include <linux/fs.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sizes.h> 20 21 #include <asm/cp15.h> 22 #include <asm/cputype.h> 23 #include <asm/sections.h> 24 #include <asm/cachetype.h> 25 #include <asm/setup.h> 26 #include <asm/smp_plat.h> 27 #include <asm/tlb.h> 28 #include <asm/highmem.h> 29 #include <asm/system_info.h> 30 #include <asm/traps.h> 31 #include <asm/procinfo.h> 32 #include <asm/memory.h> 33 34 #include <asm/mach/arch.h> 35 #include <asm/mach/map.h> 36 #include <asm/mach/pci.h> 37 38 #include "mm.h" 39 #include "tcm.h" 40 41 /* 42 * empty_zero_page is a special page that is used for 43 * zero-initialized data and COW. 44 */ 45 struct page *empty_zero_page; 46 EXPORT_SYMBOL(empty_zero_page); 47 48 /* 49 * The pmd table for the upper-most set of pages. 50 */ 51 pmd_t *top_pmd; 52 53 #define CPOLICY_UNCACHED 0 54 #define CPOLICY_BUFFERED 1 55 #define CPOLICY_WRITETHROUGH 2 56 #define CPOLICY_WRITEBACK 3 57 #define CPOLICY_WRITEALLOC 4 58 59 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 60 static unsigned int ecc_mask __initdata = 0; 61 pgprot_t pgprot_user; 62 pgprot_t pgprot_kernel; 63 pgprot_t pgprot_hyp_device; 64 pgprot_t pgprot_s2; 65 pgprot_t pgprot_s2_device; 66 67 EXPORT_SYMBOL(pgprot_user); 68 EXPORT_SYMBOL(pgprot_kernel); 69 70 struct cachepolicy { 71 const char policy[16]; 72 unsigned int cr_mask; 73 pmdval_t pmd; 74 pteval_t pte; 75 pteval_t pte_s2; 76 }; 77 78 #ifdef CONFIG_ARM_LPAE 79 #define s2_policy(policy) policy 80 #else 81 #define s2_policy(policy) 0 82 #endif 83 84 static struct cachepolicy cache_policies[] __initdata = { 85 { 86 .policy = "uncached", 87 .cr_mask = CR_W|CR_C, 88 .pmd = PMD_SECT_UNCACHED, 89 .pte = L_PTE_MT_UNCACHED, 90 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), 91 }, { 92 .policy = "buffered", 93 .cr_mask = CR_C, 94 .pmd = PMD_SECT_BUFFERED, 95 .pte = L_PTE_MT_BUFFERABLE, 96 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), 97 }, { 98 .policy = "writethrough", 99 .cr_mask = 0, 100 .pmd = PMD_SECT_WT, 101 .pte = L_PTE_MT_WRITETHROUGH, 102 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), 103 }, { 104 .policy = "writeback", 105 .cr_mask = 0, 106 .pmd = PMD_SECT_WB, 107 .pte = L_PTE_MT_WRITEBACK, 108 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), 109 }, { 110 .policy = "writealloc", 111 .cr_mask = 0, 112 .pmd = PMD_SECT_WBWA, 113 .pte = L_PTE_MT_WRITEALLOC, 114 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), 115 } 116 }; 117 118 #ifdef CONFIG_CPU_CP15 119 /* 120 * These are useful for identifying cache coherency 121 * problems by allowing the cache or the cache and 122 * writebuffer to be turned off. (Note: the write 123 * buffer should not be on and the cache off). 124 */ 125 static int __init early_cachepolicy(char *p) 126 { 127 int i; 128 129 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 130 int len = strlen(cache_policies[i].policy); 131 132 if (memcmp(p, cache_policies[i].policy, len) == 0) { 133 cachepolicy = i; 134 cr_alignment &= ~cache_policies[i].cr_mask; 135 cr_no_alignment &= ~cache_policies[i].cr_mask; 136 break; 137 } 138 } 139 if (i == ARRAY_SIZE(cache_policies)) 140 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 141 /* 142 * This restriction is partly to do with the way we boot; it is 143 * unpredictable to have memory mapped using two different sets of 144 * memory attributes (shared, type, and cache attribs). We can not 145 * change these attributes once the initial assembly has setup the 146 * page tables. 147 */ 148 if (cpu_architecture() >= CPU_ARCH_ARMv6) { 149 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); 150 cachepolicy = CPOLICY_WRITEBACK; 151 } 152 flush_cache_all(); 153 set_cr(cr_alignment); 154 return 0; 155 } 156 early_param("cachepolicy", early_cachepolicy); 157 158 static int __init early_nocache(char *__unused) 159 { 160 char *p = "buffered"; 161 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); 162 early_cachepolicy(p); 163 return 0; 164 } 165 early_param("nocache", early_nocache); 166 167 static int __init early_nowrite(char *__unused) 168 { 169 char *p = "uncached"; 170 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); 171 early_cachepolicy(p); 172 return 0; 173 } 174 early_param("nowb", early_nowrite); 175 176 #ifndef CONFIG_ARM_LPAE 177 static int __init early_ecc(char *p) 178 { 179 if (memcmp(p, "on", 2) == 0) 180 ecc_mask = PMD_PROTECTION; 181 else if (memcmp(p, "off", 3) == 0) 182 ecc_mask = 0; 183 return 0; 184 } 185 early_param("ecc", early_ecc); 186 #endif 187 188 static int __init noalign_setup(char *__unused) 189 { 190 cr_alignment &= ~CR_A; 191 cr_no_alignment &= ~CR_A; 192 set_cr(cr_alignment); 193 return 1; 194 } 195 __setup("noalign", noalign_setup); 196 197 #ifndef CONFIG_SMP 198 void adjust_cr(unsigned long mask, unsigned long set) 199 { 200 unsigned long flags; 201 202 mask &= ~CR_A; 203 204 set &= mask; 205 206 local_irq_save(flags); 207 208 cr_no_alignment = (cr_no_alignment & ~mask) | set; 209 cr_alignment = (cr_alignment & ~mask) | set; 210 211 set_cr((get_cr() & ~mask) | set); 212 213 local_irq_restore(flags); 214 } 215 #endif 216 217 #else /* ifdef CONFIG_CPU_CP15 */ 218 219 static int __init early_cachepolicy(char *p) 220 { 221 pr_warning("cachepolicy kernel parameter not supported without cp15\n"); 222 } 223 early_param("cachepolicy", early_cachepolicy); 224 225 static int __init noalign_setup(char *__unused) 226 { 227 pr_warning("noalign kernel parameter not supported without cp15\n"); 228 } 229 __setup("noalign", noalign_setup); 230 231 #endif /* ifdef CONFIG_CPU_CP15 / else */ 232 233 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN 234 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE 235 236 static struct mem_type mem_types[] = { 237 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 238 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | 239 L_PTE_SHARED, 240 .prot_l1 = PMD_TYPE_TABLE, 241 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, 242 .domain = DOMAIN_IO, 243 }, 244 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 245 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 246 .prot_l1 = PMD_TYPE_TABLE, 247 .prot_sect = PROT_SECT_DEVICE, 248 .domain = DOMAIN_IO, 249 }, 250 [MT_DEVICE_CACHED] = { /* ioremap_cached */ 251 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, 252 .prot_l1 = PMD_TYPE_TABLE, 253 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 254 .domain = DOMAIN_IO, 255 }, 256 [MT_DEVICE_WC] = { /* ioremap_wc */ 257 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 258 .prot_l1 = PMD_TYPE_TABLE, 259 .prot_sect = PROT_SECT_DEVICE, 260 .domain = DOMAIN_IO, 261 }, 262 [MT_UNCACHED] = { 263 .prot_pte = PROT_PTE_DEVICE, 264 .prot_l1 = PMD_TYPE_TABLE, 265 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 266 .domain = DOMAIN_IO, 267 }, 268 [MT_CACHECLEAN] = { 269 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 270 .domain = DOMAIN_KERNEL, 271 }, 272 #ifndef CONFIG_ARM_LPAE 273 [MT_MINICLEAN] = { 274 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 275 .domain = DOMAIN_KERNEL, 276 }, 277 #endif 278 [MT_LOW_VECTORS] = { 279 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 280 L_PTE_RDONLY, 281 .prot_l1 = PMD_TYPE_TABLE, 282 .domain = DOMAIN_USER, 283 }, 284 [MT_HIGH_VECTORS] = { 285 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 286 L_PTE_USER | L_PTE_RDONLY, 287 .prot_l1 = PMD_TYPE_TABLE, 288 .domain = DOMAIN_USER, 289 }, 290 [MT_MEMORY] = { 291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 292 .prot_l1 = PMD_TYPE_TABLE, 293 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 294 .domain = DOMAIN_KERNEL, 295 }, 296 [MT_ROM] = { 297 .prot_sect = PMD_TYPE_SECT, 298 .domain = DOMAIN_KERNEL, 299 }, 300 [MT_MEMORY_NONCACHED] = { 301 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 302 L_PTE_MT_BUFFERABLE, 303 .prot_l1 = PMD_TYPE_TABLE, 304 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 305 .domain = DOMAIN_KERNEL, 306 }, 307 [MT_MEMORY_DTCM] = { 308 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 309 L_PTE_XN, 310 .prot_l1 = PMD_TYPE_TABLE, 311 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 312 .domain = DOMAIN_KERNEL, 313 }, 314 [MT_MEMORY_ITCM] = { 315 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 316 .prot_l1 = PMD_TYPE_TABLE, 317 .domain = DOMAIN_KERNEL, 318 }, 319 [MT_MEMORY_SO] = { 320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 321 L_PTE_MT_UNCACHED | L_PTE_XN, 322 .prot_l1 = PMD_TYPE_TABLE, 323 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | 324 PMD_SECT_UNCACHED | PMD_SECT_XN, 325 .domain = DOMAIN_KERNEL, 326 }, 327 [MT_MEMORY_DMA_READY] = { 328 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 329 .prot_l1 = PMD_TYPE_TABLE, 330 .domain = DOMAIN_KERNEL, 331 }, 332 }; 333 334 const struct mem_type *get_mem_type(unsigned int type) 335 { 336 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 337 } 338 EXPORT_SYMBOL(get_mem_type); 339 340 /* 341 * Adjust the PMD section entries according to the CPU in use. 342 */ 343 static void __init build_mem_type_table(void) 344 { 345 struct cachepolicy *cp; 346 unsigned int cr = get_cr(); 347 pteval_t user_pgprot, kern_pgprot, vecs_pgprot; 348 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; 349 int cpu_arch = cpu_architecture(); 350 int i; 351 352 if (cpu_arch < CPU_ARCH_ARMv6) { 353 #if defined(CONFIG_CPU_DCACHE_DISABLE) 354 if (cachepolicy > CPOLICY_BUFFERED) 355 cachepolicy = CPOLICY_BUFFERED; 356 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 357 if (cachepolicy > CPOLICY_WRITETHROUGH) 358 cachepolicy = CPOLICY_WRITETHROUGH; 359 #endif 360 } 361 if (cpu_arch < CPU_ARCH_ARMv5) { 362 if (cachepolicy >= CPOLICY_WRITEALLOC) 363 cachepolicy = CPOLICY_WRITEBACK; 364 ecc_mask = 0; 365 } 366 if (is_smp()) 367 cachepolicy = CPOLICY_WRITEALLOC; 368 369 /* 370 * Strip out features not present on earlier architectures. 371 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those 372 * without extended page tables don't have the 'Shared' bit. 373 */ 374 if (cpu_arch < CPU_ARCH_ARMv5) 375 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 376 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); 377 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) 378 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 379 mem_types[i].prot_sect &= ~PMD_SECT_S; 380 381 /* 382 * ARMv5 and lower, bit 4 must be set for page tables (was: cache 383 * "update-able on write" bit on ARM610). However, Xscale and 384 * Xscale3 require this bit to be cleared. 385 */ 386 if (cpu_is_xscale() || cpu_is_xsc3()) { 387 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 388 mem_types[i].prot_sect &= ~PMD_BIT4; 389 mem_types[i].prot_l1 &= ~PMD_BIT4; 390 } 391 } else if (cpu_arch < CPU_ARCH_ARMv6) { 392 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 393 if (mem_types[i].prot_l1) 394 mem_types[i].prot_l1 |= PMD_BIT4; 395 if (mem_types[i].prot_sect) 396 mem_types[i].prot_sect |= PMD_BIT4; 397 } 398 } 399 400 /* 401 * Mark the device areas according to the CPU/architecture. 402 */ 403 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { 404 if (!cpu_is_xsc3()) { 405 /* 406 * Mark device regions on ARMv6+ as execute-never 407 * to prevent speculative instruction fetches. 408 */ 409 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; 410 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; 411 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; 412 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; 413 } 414 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 415 /* 416 * For ARMv7 with TEX remapping, 417 * - shared device is SXCB=1100 418 * - nonshared device is SXCB=0100 419 * - write combine device mem is SXCB=0001 420 * (Uncached Normal memory) 421 */ 422 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); 423 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); 424 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 425 } else if (cpu_is_xsc3()) { 426 /* 427 * For Xscale3, 428 * - shared device is TEXCB=00101 429 * - nonshared device is TEXCB=01000 430 * - write combine device mem is TEXCB=00100 431 * (Inner/Outer Uncacheable in xsc3 parlance) 432 */ 433 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; 434 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 435 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 436 } else { 437 /* 438 * For ARMv6 and ARMv7 without TEX remapping, 439 * - shared device is TEXCB=00001 440 * - nonshared device is TEXCB=01000 441 * - write combine device mem is TEXCB=00100 442 * (Uncached Normal in ARMv6 parlance). 443 */ 444 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 445 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 446 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 447 } 448 } else { 449 /* 450 * On others, write combining is "Uncached/Buffered" 451 */ 452 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 453 } 454 455 /* 456 * Now deal with the memory-type mappings 457 */ 458 cp = &cache_policies[cachepolicy]; 459 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 460 s2_pgprot = cp->pte_s2; 461 hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte; 462 463 /* 464 * ARMv6 and above have extended page tables. 465 */ 466 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 467 #ifndef CONFIG_ARM_LPAE 468 /* 469 * Mark cache clean areas and XIP ROM read only 470 * from SVC mode and no access from userspace. 471 */ 472 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 473 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 474 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 475 #endif 476 477 if (is_smp()) { 478 /* 479 * Mark memory with the "shared" attribute 480 * for SMP systems 481 */ 482 user_pgprot |= L_PTE_SHARED; 483 kern_pgprot |= L_PTE_SHARED; 484 vecs_pgprot |= L_PTE_SHARED; 485 s2_pgprot |= L_PTE_SHARED; 486 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; 487 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 488 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 489 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 490 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 491 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 492 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; 493 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; 494 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; 495 } 496 } 497 498 /* 499 * Non-cacheable Normal - intended for memory areas that must 500 * not cause dirty cache line writebacks when used 501 */ 502 if (cpu_arch >= CPU_ARCH_ARMv6) { 503 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 504 /* Non-cacheable Normal is XCB = 001 */ 505 mem_types[MT_MEMORY_NONCACHED].prot_sect |= 506 PMD_SECT_BUFFERED; 507 } else { 508 /* For both ARMv6 and non-TEX-remapping ARMv7 */ 509 mem_types[MT_MEMORY_NONCACHED].prot_sect |= 510 PMD_SECT_TEX(1); 511 } 512 } else { 513 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; 514 } 515 516 #ifdef CONFIG_ARM_LPAE 517 /* 518 * Do not generate access flag faults for the kernel mappings. 519 */ 520 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 521 mem_types[i].prot_pte |= PTE_EXT_AF; 522 if (mem_types[i].prot_sect) 523 mem_types[i].prot_sect |= PMD_SECT_AF; 524 } 525 kern_pgprot |= PTE_EXT_AF; 526 vecs_pgprot |= PTE_EXT_AF; 527 #endif 528 529 for (i = 0; i < 16; i++) { 530 pteval_t v = pgprot_val(protection_map[i]); 531 protection_map[i] = __pgprot(v | user_pgprot); 532 } 533 534 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; 535 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; 536 537 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 538 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 539 L_PTE_DIRTY | kern_pgprot); 540 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); 541 pgprot_s2_device = __pgprot(s2_device_pgprot); 542 pgprot_hyp_device = __pgprot(hyp_device_pgprot); 543 544 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 545 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 546 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; 547 mem_types[MT_MEMORY].prot_pte |= kern_pgprot; 548 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; 549 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; 550 mem_types[MT_ROM].prot_sect |= cp->pmd; 551 552 switch (cp->pmd) { 553 case PMD_SECT_WT: 554 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 555 break; 556 case PMD_SECT_WB: 557 case PMD_SECT_WBWA: 558 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 559 break; 560 } 561 pr_info("Memory policy: %sData cache %s\n", 562 ecc_mask ? "ECC enabled, " : "", cp->policy); 563 564 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 565 struct mem_type *t = &mem_types[i]; 566 if (t->prot_l1) 567 t->prot_l1 |= PMD_DOMAIN(t->domain); 568 if (t->prot_sect) 569 t->prot_sect |= PMD_DOMAIN(t->domain); 570 } 571 } 572 573 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 574 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 575 unsigned long size, pgprot_t vma_prot) 576 { 577 if (!pfn_valid(pfn)) 578 return pgprot_noncached(vma_prot); 579 else if (file->f_flags & O_SYNC) 580 return pgprot_writecombine(vma_prot); 581 return vma_prot; 582 } 583 EXPORT_SYMBOL(phys_mem_access_prot); 584 #endif 585 586 #define vectors_base() (vectors_high() ? 0xffff0000 : 0) 587 588 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) 589 { 590 void *ptr = __va(memblock_alloc(sz, align)); 591 memset(ptr, 0, sz); 592 return ptr; 593 } 594 595 static void __init *early_alloc(unsigned long sz) 596 { 597 return early_alloc_aligned(sz, sz); 598 } 599 600 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) 601 { 602 if (pmd_none(*pmd)) { 603 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); 604 __pmd_populate(pmd, __pa(pte), prot); 605 } 606 BUG_ON(pmd_bad(*pmd)); 607 return pte_offset_kernel(pmd, addr); 608 } 609 610 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 611 unsigned long end, unsigned long pfn, 612 const struct mem_type *type) 613 { 614 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); 615 do { 616 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); 617 pfn++; 618 } while (pte++, addr += PAGE_SIZE, addr != end); 619 } 620 621 static void __init __map_init_section(pmd_t *pmd, unsigned long addr, 622 unsigned long end, phys_addr_t phys, 623 const struct mem_type *type) 624 { 625 pmd_t *p = pmd; 626 627 #ifndef CONFIG_ARM_LPAE 628 /* 629 * In classic MMU format, puds and pmds are folded in to 630 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a 631 * group of L1 entries making up one logical pointer to 632 * an L2 table (2MB), where as PMDs refer to the individual 633 * L1 entries (1MB). Hence increment to get the correct 634 * offset for odd 1MB sections. 635 * (See arch/arm/include/asm/pgtable-2level.h) 636 */ 637 if (addr & SECTION_SIZE) 638 pmd++; 639 #endif 640 do { 641 *pmd = __pmd(phys | type->prot_sect); 642 phys += SECTION_SIZE; 643 } while (pmd++, addr += SECTION_SIZE, addr != end); 644 645 flush_pmd_entry(p); 646 } 647 648 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, 649 unsigned long end, phys_addr_t phys, 650 const struct mem_type *type) 651 { 652 pmd_t *pmd = pmd_offset(pud, addr); 653 unsigned long next; 654 655 do { 656 /* 657 * With LPAE, we must loop over to map 658 * all the pmds for the given range. 659 */ 660 next = pmd_addr_end(addr, end); 661 662 /* 663 * Try a section mapping - addr, next and phys must all be 664 * aligned to a section boundary. 665 */ 666 if (type->prot_sect && 667 ((addr | next | phys) & ~SECTION_MASK) == 0) { 668 __map_init_section(pmd, addr, next, phys, type); 669 } else { 670 alloc_init_pte(pmd, addr, next, 671 __phys_to_pfn(phys), type); 672 } 673 674 phys += next - addr; 675 676 } while (pmd++, addr = next, addr != end); 677 } 678 679 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 680 unsigned long end, phys_addr_t phys, 681 const struct mem_type *type) 682 { 683 pud_t *pud = pud_offset(pgd, addr); 684 unsigned long next; 685 686 do { 687 next = pud_addr_end(addr, end); 688 alloc_init_pmd(pud, addr, next, phys, type); 689 phys += next - addr; 690 } while (pud++, addr = next, addr != end); 691 } 692 693 #ifndef CONFIG_ARM_LPAE 694 static void __init create_36bit_mapping(struct map_desc *md, 695 const struct mem_type *type) 696 { 697 unsigned long addr, length, end; 698 phys_addr_t phys; 699 pgd_t *pgd; 700 701 addr = md->virtual; 702 phys = __pfn_to_phys(md->pfn); 703 length = PAGE_ALIGN(md->length); 704 705 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 706 printk(KERN_ERR "MM: CPU does not support supersection " 707 "mapping for 0x%08llx at 0x%08lx\n", 708 (long long)__pfn_to_phys((u64)md->pfn), addr); 709 return; 710 } 711 712 /* N.B. ARMv6 supersections are only defined to work with domain 0. 713 * Since domain assignments can in fact be arbitrary, the 714 * 'domain == 0' check below is required to insure that ARMv6 715 * supersections are only allocated for domain 0 regardless 716 * of the actual domain assignments in use. 717 */ 718 if (type->domain) { 719 printk(KERN_ERR "MM: invalid domain in supersection " 720 "mapping for 0x%08llx at 0x%08lx\n", 721 (long long)__pfn_to_phys((u64)md->pfn), addr); 722 return; 723 } 724 725 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 726 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" 727 " at 0x%08lx invalid alignment\n", 728 (long long)__pfn_to_phys((u64)md->pfn), addr); 729 return; 730 } 731 732 /* 733 * Shift bits [35:32] of address into bits [23:20] of PMD 734 * (See ARMv6 spec). 735 */ 736 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 737 738 pgd = pgd_offset_k(addr); 739 end = addr + length; 740 do { 741 pud_t *pud = pud_offset(pgd, addr); 742 pmd_t *pmd = pmd_offset(pud, addr); 743 int i; 744 745 for (i = 0; i < 16; i++) 746 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); 747 748 addr += SUPERSECTION_SIZE; 749 phys += SUPERSECTION_SIZE; 750 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 751 } while (addr != end); 752 } 753 #endif /* !CONFIG_ARM_LPAE */ 754 755 /* 756 * Create the page directory entries and any necessary 757 * page tables for the mapping specified by `md'. We 758 * are able to cope here with varying sizes and address 759 * offsets, and we take full advantage of sections and 760 * supersections. 761 */ 762 static void __init create_mapping(struct map_desc *md) 763 { 764 unsigned long addr, length, end; 765 phys_addr_t phys; 766 const struct mem_type *type; 767 pgd_t *pgd; 768 769 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 770 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" 771 " at 0x%08lx in user region\n", 772 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 773 return; 774 } 775 776 if ((md->type == MT_DEVICE || md->type == MT_ROM) && 777 md->virtual >= PAGE_OFFSET && 778 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { 779 printk(KERN_WARNING "BUG: mapping for 0x%08llx" 780 " at 0x%08lx out of vmalloc space\n", 781 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 782 } 783 784 type = &mem_types[md->type]; 785 786 #ifndef CONFIG_ARM_LPAE 787 /* 788 * Catch 36-bit addresses 789 */ 790 if (md->pfn >= 0x100000) { 791 create_36bit_mapping(md, type); 792 return; 793 } 794 #endif 795 796 addr = md->virtual & PAGE_MASK; 797 phys = __pfn_to_phys(md->pfn); 798 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 799 800 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 801 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " 802 "be mapped using pages, ignoring.\n", 803 (long long)__pfn_to_phys(md->pfn), addr); 804 return; 805 } 806 807 pgd = pgd_offset_k(addr); 808 end = addr + length; 809 do { 810 unsigned long next = pgd_addr_end(addr, end); 811 812 alloc_init_pud(pgd, addr, next, phys, type); 813 814 phys += next - addr; 815 addr = next; 816 } while (pgd++, addr != end); 817 } 818 819 /* 820 * Create the architecture specific mappings 821 */ 822 void __init iotable_init(struct map_desc *io_desc, int nr) 823 { 824 struct map_desc *md; 825 struct vm_struct *vm; 826 struct static_vm *svm; 827 828 if (!nr) 829 return; 830 831 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm)); 832 833 for (md = io_desc; nr; md++, nr--) { 834 create_mapping(md); 835 836 vm = &svm->vm; 837 vm->addr = (void *)(md->virtual & PAGE_MASK); 838 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 839 vm->phys_addr = __pfn_to_phys(md->pfn); 840 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 841 vm->flags |= VM_ARM_MTYPE(md->type); 842 vm->caller = iotable_init; 843 add_static_vm_early(svm++); 844 } 845 } 846 847 void __init vm_reserve_area_early(unsigned long addr, unsigned long size, 848 void *caller) 849 { 850 struct vm_struct *vm; 851 struct static_vm *svm; 852 853 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm)); 854 855 vm = &svm->vm; 856 vm->addr = (void *)addr; 857 vm->size = size; 858 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; 859 vm->caller = caller; 860 add_static_vm_early(svm); 861 } 862 863 #ifndef CONFIG_ARM_LPAE 864 865 /* 866 * The Linux PMD is made of two consecutive section entries covering 2MB 867 * (see definition in include/asm/pgtable-2level.h). However a call to 868 * create_mapping() may optimize static mappings by using individual 869 * 1MB section mappings. This leaves the actual PMD potentially half 870 * initialized if the top or bottom section entry isn't used, leaving it 871 * open to problems if a subsequent ioremap() or vmalloc() tries to use 872 * the virtual space left free by that unused section entry. 873 * 874 * Let's avoid the issue by inserting dummy vm entries covering the unused 875 * PMD halves once the static mappings are in place. 876 */ 877 878 static void __init pmd_empty_section_gap(unsigned long addr) 879 { 880 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); 881 } 882 883 static void __init fill_pmd_gaps(void) 884 { 885 struct static_vm *svm; 886 struct vm_struct *vm; 887 unsigned long addr, next = 0; 888 pmd_t *pmd; 889 890 list_for_each_entry(svm, &static_vmlist, list) { 891 vm = &svm->vm; 892 addr = (unsigned long)vm->addr; 893 if (addr < next) 894 continue; 895 896 /* 897 * Check if this vm starts on an odd section boundary. 898 * If so and the first section entry for this PMD is free 899 * then we block the corresponding virtual address. 900 */ 901 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 902 pmd = pmd_off_k(addr); 903 if (pmd_none(*pmd)) 904 pmd_empty_section_gap(addr & PMD_MASK); 905 } 906 907 /* 908 * Then check if this vm ends on an odd section boundary. 909 * If so and the second section entry for this PMD is empty 910 * then we block the corresponding virtual address. 911 */ 912 addr += vm->size; 913 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 914 pmd = pmd_off_k(addr) + 1; 915 if (pmd_none(*pmd)) 916 pmd_empty_section_gap(addr); 917 } 918 919 /* no need to look at any vm entry until we hit the next PMD */ 920 next = (addr + PMD_SIZE - 1) & PMD_MASK; 921 } 922 } 923 924 #else 925 #define fill_pmd_gaps() do { } while (0) 926 #endif 927 928 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) 929 static void __init pci_reserve_io(void) 930 { 931 struct static_vm *svm; 932 933 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); 934 if (svm) 935 return; 936 937 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); 938 } 939 #else 940 #define pci_reserve_io() do { } while (0) 941 #endif 942 943 #ifdef CONFIG_DEBUG_LL 944 void __init debug_ll_io_init(void) 945 { 946 struct map_desc map; 947 948 debug_ll_addr(&map.pfn, &map.virtual); 949 if (!map.pfn || !map.virtual) 950 return; 951 map.pfn = __phys_to_pfn(map.pfn); 952 map.virtual &= PAGE_MASK; 953 map.length = PAGE_SIZE; 954 map.type = MT_DEVICE; 955 iotable_init(&map, 1); 956 } 957 #endif 958 959 static void * __initdata vmalloc_min = 960 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); 961 962 /* 963 * vmalloc=size forces the vmalloc area to be exactly 'size' 964 * bytes. This can be used to increase (or decrease) the vmalloc 965 * area - the default is 240m. 966 */ 967 static int __init early_vmalloc(char *arg) 968 { 969 unsigned long vmalloc_reserve = memparse(arg, NULL); 970 971 if (vmalloc_reserve < SZ_16M) { 972 vmalloc_reserve = SZ_16M; 973 printk(KERN_WARNING 974 "vmalloc area too small, limiting to %luMB\n", 975 vmalloc_reserve >> 20); 976 } 977 978 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { 979 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); 980 printk(KERN_WARNING 981 "vmalloc area is too big, limiting to %luMB\n", 982 vmalloc_reserve >> 20); 983 } 984 985 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); 986 return 0; 987 } 988 early_param("vmalloc", early_vmalloc); 989 990 phys_addr_t arm_lowmem_limit __initdata = 0; 991 992 void __init sanity_check_meminfo(void) 993 { 994 phys_addr_t memblock_limit = 0; 995 int i, j, highmem = 0; 996 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1; 997 998 for (i = 0, j = 0; i < meminfo.nr_banks; i++) { 999 struct membank *bank = &meminfo.bank[j]; 1000 phys_addr_t size_limit; 1001 1002 *bank = meminfo.bank[i]; 1003 size_limit = bank->size; 1004 1005 if (bank->start >= vmalloc_limit) 1006 highmem = 1; 1007 else 1008 size_limit = vmalloc_limit - bank->start; 1009 1010 bank->highmem = highmem; 1011 1012 #ifdef CONFIG_HIGHMEM 1013 /* 1014 * Split those memory banks which are partially overlapping 1015 * the vmalloc area greatly simplifying things later. 1016 */ 1017 if (!highmem && bank->size > size_limit) { 1018 if (meminfo.nr_banks >= NR_BANKS) { 1019 printk(KERN_CRIT "NR_BANKS too low, " 1020 "ignoring high memory\n"); 1021 } else { 1022 memmove(bank + 1, bank, 1023 (meminfo.nr_banks - i) * sizeof(*bank)); 1024 meminfo.nr_banks++; 1025 i++; 1026 bank[1].size -= size_limit; 1027 bank[1].start = vmalloc_limit; 1028 bank[1].highmem = highmem = 1; 1029 j++; 1030 } 1031 bank->size = size_limit; 1032 } 1033 #else 1034 /* 1035 * Highmem banks not allowed with !CONFIG_HIGHMEM. 1036 */ 1037 if (highmem) { 1038 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " 1039 "(!CONFIG_HIGHMEM).\n", 1040 (unsigned long long)bank->start, 1041 (unsigned long long)bank->start + bank->size - 1); 1042 continue; 1043 } 1044 1045 /* 1046 * Check whether this memory bank would partially overlap 1047 * the vmalloc area. 1048 */ 1049 if (bank->size > size_limit) { 1050 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " 1051 "to -%.8llx (vmalloc region overlap).\n", 1052 (unsigned long long)bank->start, 1053 (unsigned long long)bank->start + bank->size - 1, 1054 (unsigned long long)bank->start + size_limit - 1); 1055 bank->size = size_limit; 1056 } 1057 #endif 1058 if (!bank->highmem) { 1059 phys_addr_t bank_end = bank->start + bank->size; 1060 1061 if (bank_end > arm_lowmem_limit) 1062 arm_lowmem_limit = bank_end; 1063 1064 /* 1065 * Find the first non-section-aligned page, and point 1066 * memblock_limit at it. This relies on rounding the 1067 * limit down to be section-aligned, which happens at 1068 * the end of this function. 1069 * 1070 * With this algorithm, the start or end of almost any 1071 * bank can be non-section-aligned. The only exception 1072 * is that the start of the bank 0 must be section- 1073 * aligned, since otherwise memory would need to be 1074 * allocated when mapping the start of bank 0, which 1075 * occurs before any free memory is mapped. 1076 */ 1077 if (!memblock_limit) { 1078 if (!IS_ALIGNED(bank->start, SECTION_SIZE)) 1079 memblock_limit = bank->start; 1080 else if (!IS_ALIGNED(bank_end, SECTION_SIZE)) 1081 memblock_limit = bank_end; 1082 } 1083 } 1084 j++; 1085 } 1086 #ifdef CONFIG_HIGHMEM 1087 if (highmem) { 1088 const char *reason = NULL; 1089 1090 if (cache_is_vipt_aliasing()) { 1091 /* 1092 * Interactions between kmap and other mappings 1093 * make highmem support with aliasing VIPT caches 1094 * rather difficult. 1095 */ 1096 reason = "with VIPT aliasing cache"; 1097 } 1098 if (reason) { 1099 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", 1100 reason); 1101 while (j > 0 && meminfo.bank[j - 1].highmem) 1102 j--; 1103 } 1104 } 1105 #endif 1106 meminfo.nr_banks = j; 1107 high_memory = __va(arm_lowmem_limit - 1) + 1; 1108 1109 /* 1110 * Round the memblock limit down to a section size. This 1111 * helps to ensure that we will allocate memory from the 1112 * last full section, which should be mapped. 1113 */ 1114 if (memblock_limit) 1115 memblock_limit = round_down(memblock_limit, SECTION_SIZE); 1116 if (!memblock_limit) 1117 memblock_limit = arm_lowmem_limit; 1118 1119 memblock_set_current_limit(memblock_limit); 1120 } 1121 1122 static inline void prepare_page_table(void) 1123 { 1124 unsigned long addr; 1125 phys_addr_t end; 1126 1127 /* 1128 * Clear out all the mappings below the kernel image. 1129 */ 1130 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) 1131 pmd_clear(pmd_off_k(addr)); 1132 1133 #ifdef CONFIG_XIP_KERNEL 1134 /* The XIP kernel is mapped in the module area -- skip over it */ 1135 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; 1136 #endif 1137 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) 1138 pmd_clear(pmd_off_k(addr)); 1139 1140 /* 1141 * Find the end of the first block of lowmem. 1142 */ 1143 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; 1144 if (end >= arm_lowmem_limit) 1145 end = arm_lowmem_limit; 1146 1147 /* 1148 * Clear out all the kernel space mappings, except for the first 1149 * memory bank, up to the vmalloc region. 1150 */ 1151 for (addr = __phys_to_virt(end); 1152 addr < VMALLOC_START; addr += PMD_SIZE) 1153 pmd_clear(pmd_off_k(addr)); 1154 } 1155 1156 #ifdef CONFIG_ARM_LPAE 1157 /* the first page is reserved for pgd */ 1158 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ 1159 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) 1160 #else 1161 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) 1162 #endif 1163 1164 /* 1165 * Reserve the special regions of memory 1166 */ 1167 void __init arm_mm_memblock_reserve(void) 1168 { 1169 /* 1170 * Reserve the page tables. These are already in use, 1171 * and can only be in node 0. 1172 */ 1173 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); 1174 1175 #ifdef CONFIG_SA1111 1176 /* 1177 * Because of the SA1111 DMA bug, we want to preserve our 1178 * precious DMA-able memory... 1179 */ 1180 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); 1181 #endif 1182 } 1183 1184 /* 1185 * Set up the device mappings. Since we clear out the page tables for all 1186 * mappings above VMALLOC_START, we will remove any debug device mappings. 1187 * This means you have to be careful how you debug this function, or any 1188 * called function. This means you can't use any function or debugging 1189 * method which may touch any device, otherwise the kernel _will_ crash. 1190 */ 1191 static void __init devicemaps_init(const struct machine_desc *mdesc) 1192 { 1193 struct map_desc map; 1194 unsigned long addr; 1195 void *vectors; 1196 1197 /* 1198 * Allocate the vector page early. 1199 */ 1200 vectors = early_alloc(PAGE_SIZE * 2); 1201 1202 early_trap_init(vectors); 1203 1204 for (addr = VMALLOC_START; addr; addr += PMD_SIZE) 1205 pmd_clear(pmd_off_k(addr)); 1206 1207 /* 1208 * Map the kernel if it is XIP. 1209 * It is always first in the modulearea. 1210 */ 1211 #ifdef CONFIG_XIP_KERNEL 1212 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 1213 map.virtual = MODULES_VADDR; 1214 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; 1215 map.type = MT_ROM; 1216 create_mapping(&map); 1217 #endif 1218 1219 /* 1220 * Map the cache flushing regions. 1221 */ 1222 #ifdef FLUSH_BASE 1223 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 1224 map.virtual = FLUSH_BASE; 1225 map.length = SZ_1M; 1226 map.type = MT_CACHECLEAN; 1227 create_mapping(&map); 1228 #endif 1229 #ifdef FLUSH_BASE_MINICACHE 1230 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 1231 map.virtual = FLUSH_BASE_MINICACHE; 1232 map.length = SZ_1M; 1233 map.type = MT_MINICLEAN; 1234 create_mapping(&map); 1235 #endif 1236 1237 /* 1238 * Create a mapping for the machine vectors at the high-vectors 1239 * location (0xffff0000). If we aren't using high-vectors, also 1240 * create a mapping at the low-vectors virtual address. 1241 */ 1242 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 1243 map.virtual = 0xffff0000; 1244 map.length = PAGE_SIZE; 1245 #ifdef CONFIG_KUSER_HELPERS 1246 map.type = MT_HIGH_VECTORS; 1247 #else 1248 map.type = MT_LOW_VECTORS; 1249 #endif 1250 create_mapping(&map); 1251 1252 if (!vectors_high()) { 1253 map.virtual = 0; 1254 map.length = PAGE_SIZE * 2; 1255 map.type = MT_LOW_VECTORS; 1256 create_mapping(&map); 1257 } 1258 1259 /* Now create a kernel read-only mapping */ 1260 map.pfn += 1; 1261 map.virtual = 0xffff0000 + PAGE_SIZE; 1262 map.length = PAGE_SIZE; 1263 map.type = MT_LOW_VECTORS; 1264 create_mapping(&map); 1265 1266 /* 1267 * Ask the machine support to map in the statically mapped devices. 1268 */ 1269 if (mdesc->map_io) 1270 mdesc->map_io(); 1271 else 1272 debug_ll_io_init(); 1273 fill_pmd_gaps(); 1274 1275 /* Reserve fixed i/o space in VMALLOC region */ 1276 pci_reserve_io(); 1277 1278 /* 1279 * Finally flush the caches and tlb to ensure that we're in a 1280 * consistent state wrt the writebuffer. This also ensures that 1281 * any write-allocated cache lines in the vector page are written 1282 * back. After this point, we can start to touch devices again. 1283 */ 1284 local_flush_tlb_all(); 1285 flush_cache_all(); 1286 } 1287 1288 static void __init kmap_init(void) 1289 { 1290 #ifdef CONFIG_HIGHMEM 1291 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), 1292 PKMAP_BASE, _PAGE_KERNEL_TABLE); 1293 #endif 1294 } 1295 1296 static void __init map_lowmem(void) 1297 { 1298 struct memblock_region *reg; 1299 1300 /* Map all the lowmem memory banks. */ 1301 for_each_memblock(memory, reg) { 1302 phys_addr_t start = reg->base; 1303 phys_addr_t end = start + reg->size; 1304 struct map_desc map; 1305 1306 if (end > arm_lowmem_limit) 1307 end = arm_lowmem_limit; 1308 if (start >= end) 1309 break; 1310 1311 map.pfn = __phys_to_pfn(start); 1312 map.virtual = __phys_to_virt(start); 1313 map.length = end - start; 1314 map.type = MT_MEMORY; 1315 1316 create_mapping(&map); 1317 } 1318 } 1319 1320 #ifdef CONFIG_ARM_LPAE 1321 /* 1322 * early_paging_init() recreates boot time page table setup, allowing machines 1323 * to switch over to a high (>4G) address space on LPAE systems 1324 */ 1325 void __init early_paging_init(const struct machine_desc *mdesc, 1326 struct proc_info_list *procinfo) 1327 { 1328 pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags; 1329 unsigned long map_start, map_end; 1330 pgd_t *pgd0, *pgdk; 1331 pud_t *pud0, *pudk, *pud_start; 1332 pmd_t *pmd0, *pmdk; 1333 phys_addr_t phys; 1334 int i; 1335 1336 if (!(mdesc->init_meminfo)) 1337 return; 1338 1339 /* remap kernel code and data */ 1340 map_start = init_mm.start_code; 1341 map_end = init_mm.brk; 1342 1343 /* get a handle on things... */ 1344 pgd0 = pgd_offset_k(0); 1345 pud_start = pud0 = pud_offset(pgd0, 0); 1346 pmd0 = pmd_offset(pud0, 0); 1347 1348 pgdk = pgd_offset_k(map_start); 1349 pudk = pud_offset(pgdk, map_start); 1350 pmdk = pmd_offset(pudk, map_start); 1351 1352 mdesc->init_meminfo(); 1353 1354 /* Run the patch stub to update the constants */ 1355 fixup_pv_table(&__pv_table_begin, 1356 (&__pv_table_end - &__pv_table_begin) << 2); 1357 1358 /* 1359 * Cache cleaning operations for self-modifying code 1360 * We should clean the entries by MVA but running a 1361 * for loop over every pv_table entry pointer would 1362 * just complicate the code. 1363 */ 1364 flush_cache_louis(); 1365 dsb(); 1366 isb(); 1367 1368 /* remap level 1 table */ 1369 for (i = 0; i < PTRS_PER_PGD; pud0++, i++) { 1370 set_pud(pud0, 1371 __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER)); 1372 pmd0 += PTRS_PER_PMD; 1373 } 1374 1375 /* remap pmds for kernel mapping */ 1376 phys = __pa(map_start) & PMD_MASK; 1377 do { 1378 *pmdk++ = __pmd(phys | pmdprot); 1379 phys += PMD_SIZE; 1380 } while (phys < map_end); 1381 1382 flush_cache_all(); 1383 cpu_switch_mm(pgd0, &init_mm); 1384 cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET); 1385 local_flush_bp_all(); 1386 local_flush_tlb_all(); 1387 } 1388 1389 #else 1390 1391 void __init early_paging_init(const struct machine_desc *mdesc, 1392 struct proc_info_list *procinfo) 1393 { 1394 if (mdesc->init_meminfo) 1395 mdesc->init_meminfo(); 1396 } 1397 1398 #endif 1399 1400 /* 1401 * paging_init() sets up the page tables, initialises the zone memory 1402 * maps, and sets up the zero page, bad page and bad page tables. 1403 */ 1404 void __init paging_init(const struct machine_desc *mdesc) 1405 { 1406 void *zero_page; 1407 1408 build_mem_type_table(); 1409 prepare_page_table(); 1410 map_lowmem(); 1411 dma_contiguous_remap(); 1412 devicemaps_init(mdesc); 1413 kmap_init(); 1414 tcm_init(); 1415 1416 top_pmd = pmd_off_k(0xffff0000); 1417 1418 /* allocate the zero page. */ 1419 zero_page = early_alloc(PAGE_SIZE); 1420 1421 bootmem_init(); 1422 1423 empty_zero_page = virt_to_page(zero_page); 1424 __flush_dcache_page(NULL, empty_zero_page); 1425 } 1426