1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mm/fault-armv.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Modifications for ARM processor (c) 1995-2002 Russell King 7 */ 8 #include <linux/sched.h> 9 #include <linux/kernel.h> 10 #include <linux/mm.h> 11 #include <linux/bitops.h> 12 #include <linux/vmalloc.h> 13 #include <linux/init.h> 14 #include <linux/pagemap.h> 15 #include <linux/gfp.h> 16 17 #include <asm/bugs.h> 18 #include <asm/cacheflush.h> 19 #include <asm/cachetype.h> 20 #include <asm/tlbflush.h> 21 22 #include "mm.h" 23 24 static pteval_t shared_pte_mask = L_PTE_MT_BUFFERABLE; 25 26 #if __LINUX_ARM_ARCH__ < 6 27 /* 28 * We take the easy way out of this problem - we make the 29 * PTE uncacheable. However, we leave the write buffer on. 30 * 31 * Note that the pte lock held when calling update_mmu_cache must also 32 * guard the pte (somewhere else in the same mm) that we modify here. 33 * Therefore those configurations which might call adjust_pte (those 34 * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock. 35 */ 36 static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address, 37 unsigned long pfn, pte_t *ptep) 38 { 39 pte_t entry = *ptep; 40 int ret; 41 42 /* 43 * If this page is present, it's actually being shared. 44 */ 45 ret = pte_present(entry); 46 47 /* 48 * If this page isn't present, or is already setup to 49 * fault (ie, is old), we can safely ignore any issues. 50 */ 51 if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) { 52 flush_cache_page(vma, address, pfn); 53 outer_flush_range((pfn << PAGE_SHIFT), 54 (pfn << PAGE_SHIFT) + PAGE_SIZE); 55 pte_val(entry) &= ~L_PTE_MT_MASK; 56 pte_val(entry) |= shared_pte_mask; 57 set_pte_at(vma->vm_mm, address, ptep, entry); 58 flush_tlb_page(vma, address); 59 } 60 61 return ret; 62 } 63 64 #if USE_SPLIT_PTE_PTLOCKS 65 /* 66 * If we are using split PTE locks, then we need to take the page 67 * lock here. Otherwise we are using shared mm->page_table_lock 68 * which is already locked, thus cannot take it. 69 */ 70 static inline void do_pte_lock(spinlock_t *ptl) 71 { 72 /* 73 * Use nested version here to indicate that we are already 74 * holding one similar spinlock. 75 */ 76 spin_lock_nested(ptl, SINGLE_DEPTH_NESTING); 77 } 78 79 static inline void do_pte_unlock(spinlock_t *ptl) 80 { 81 spin_unlock(ptl); 82 } 83 #else /* !USE_SPLIT_PTE_PTLOCKS */ 84 static inline void do_pte_lock(spinlock_t *ptl) {} 85 static inline void do_pte_unlock(spinlock_t *ptl) {} 86 #endif /* USE_SPLIT_PTE_PTLOCKS */ 87 88 static int adjust_pte(struct vm_area_struct *vma, unsigned long address, 89 unsigned long pfn) 90 { 91 spinlock_t *ptl; 92 pgd_t *pgd; 93 p4d_t *p4d; 94 pud_t *pud; 95 pmd_t *pmd; 96 pte_t *pte; 97 int ret; 98 99 pgd = pgd_offset(vma->vm_mm, address); 100 if (pgd_none_or_clear_bad(pgd)) 101 return 0; 102 103 p4d = p4d_offset(pgd, address); 104 if (p4d_none_or_clear_bad(p4d)) 105 return 0; 106 107 pud = pud_offset(p4d, address); 108 if (pud_none_or_clear_bad(pud)) 109 return 0; 110 111 pmd = pmd_offset(pud, address); 112 if (pmd_none_or_clear_bad(pmd)) 113 return 0; 114 115 /* 116 * This is called while another page table is mapped, so we 117 * must use the nested version. This also means we need to 118 * open-code the spin-locking. 119 */ 120 pte = pte_offset_map(pmd, address); 121 if (!pte) 122 return 0; 123 124 ptl = pte_lockptr(vma->vm_mm, pmd); 125 do_pte_lock(ptl); 126 127 ret = do_adjust_pte(vma, address, pfn, pte); 128 129 do_pte_unlock(ptl); 130 pte_unmap(pte); 131 132 return ret; 133 } 134 135 static void 136 make_coherent(struct address_space *mapping, struct vm_area_struct *vma, 137 unsigned long addr, pte_t *ptep, unsigned long pfn) 138 { 139 struct mm_struct *mm = vma->vm_mm; 140 struct vm_area_struct *mpnt; 141 unsigned long offset; 142 pgoff_t pgoff; 143 int aliases = 0; 144 145 pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT); 146 147 /* 148 * If we have any shared mappings that are in the same mm 149 * space, then we need to handle them specially to maintain 150 * cache coherency. 151 */ 152 flush_dcache_mmap_lock(mapping); 153 vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) { 154 /* 155 * If this VMA is not in our MM, we can ignore it. 156 * Note that we intentionally mask out the VMA 157 * that we are fixing up. 158 */ 159 if (mpnt->vm_mm != mm || mpnt == vma) 160 continue; 161 if (!(mpnt->vm_flags & VM_MAYSHARE)) 162 continue; 163 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; 164 aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn); 165 } 166 flush_dcache_mmap_unlock(mapping); 167 if (aliases) 168 do_adjust_pte(vma, addr, pfn, ptep); 169 } 170 171 /* 172 * Take care of architecture specific things when placing a new PTE into 173 * a page table, or changing an existing PTE. Basically, there are two 174 * things that we need to take care of: 175 * 176 * 1. If PG_dcache_clean is not set for the page, we need to ensure 177 * that any cache entries for the kernels virtual memory 178 * range are written back to the page. 179 * 2. If we have multiple shared mappings of the same space in 180 * an object, we need to deal with the cache aliasing issues. 181 * 182 * Note that the pte lock will be held. 183 */ 184 void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, 185 pte_t *ptep) 186 { 187 unsigned long pfn = pte_pfn(*ptep); 188 struct address_space *mapping; 189 struct page *page; 190 191 if (!pfn_valid(pfn)) 192 return; 193 194 /* 195 * The zero page is never written to, so never has any dirty 196 * cache lines, and therefore never needs to be flushed. 197 */ 198 page = pfn_to_page(pfn); 199 if (page == ZERO_PAGE(0)) 200 return; 201 202 mapping = page_mapping_file(page); 203 if (!test_and_set_bit(PG_dcache_clean, &page->flags)) 204 __flush_dcache_page(mapping, page); 205 if (mapping) { 206 if (cache_is_vivt()) 207 make_coherent(mapping, vma, addr, ptep, pfn); 208 else if (vma->vm_flags & VM_EXEC) 209 __flush_icache_all(); 210 } 211 } 212 #endif /* __LINUX_ARM_ARCH__ < 6 */ 213 214 /* 215 * Check whether the write buffer has physical address aliasing 216 * issues. If it has, we need to avoid them for the case where 217 * we have several shared mappings of the same object in user 218 * space. 219 */ 220 static int __init check_writebuffer(unsigned long *p1, unsigned long *p2) 221 { 222 register unsigned long zero = 0, one = 1, val; 223 224 local_irq_disable(); 225 mb(); 226 *p1 = one; 227 mb(); 228 *p2 = zero; 229 mb(); 230 val = *p1; 231 mb(); 232 local_irq_enable(); 233 return val != zero; 234 } 235 236 void __init check_writebuffer_bugs(void) 237 { 238 struct page *page; 239 const char *reason; 240 unsigned long v = 1; 241 242 pr_info("CPU: Testing write buffer coherency: "); 243 244 page = alloc_page(GFP_KERNEL); 245 if (page) { 246 unsigned long *p1, *p2; 247 pgprot_t prot = __pgprot_modify(PAGE_KERNEL, 248 L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE); 249 250 p1 = vmap(&page, 1, VM_IOREMAP, prot); 251 p2 = vmap(&page, 1, VM_IOREMAP, prot); 252 253 if (p1 && p2) { 254 v = check_writebuffer(p1, p2); 255 reason = "enabling work-around"; 256 } else { 257 reason = "unable to map memory\n"; 258 } 259 260 vunmap(p1); 261 vunmap(p2); 262 put_page(page); 263 } else { 264 reason = "unable to grab page\n"; 265 } 266 267 if (v) { 268 pr_cont("failed, %s\n", reason); 269 shared_pte_mask = L_PTE_MT_UNCACHED; 270 } else { 271 pr_cont("ok\n"); 272 } 273 } 274