1 /* 2 * linux/arch/arm/mm/context.c 3 * 4 * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/init.h> 11 #include <linux/sched.h> 12 #include <linux/mm.h> 13 #include <linux/smp.h> 14 #include <linux/percpu.h> 15 16 #include <asm/mmu_context.h> 17 #include <asm/thread_notify.h> 18 #include <asm/tlbflush.h> 19 20 static DEFINE_RAW_SPINLOCK(cpu_asid_lock); 21 unsigned int cpu_last_asid = ASID_FIRST_VERSION; 22 23 #ifdef CONFIG_ARM_LPAE 24 void cpu_set_reserved_ttbr0(void) 25 { 26 unsigned long ttbl = __pa(swapper_pg_dir); 27 unsigned long ttbh = 0; 28 29 /* 30 * Set TTBR0 to swapper_pg_dir which contains only global entries. The 31 * ASID is set to 0. 32 */ 33 asm volatile( 34 " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" 35 : 36 : "r" (ttbl), "r" (ttbh)); 37 isb(); 38 } 39 #else 40 void cpu_set_reserved_ttbr0(void) 41 { 42 u32 ttb; 43 /* Copy TTBR1 into TTBR0 */ 44 asm volatile( 45 " mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n" 46 " mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n" 47 : "=r" (ttb)); 48 isb(); 49 } 50 #endif 51 52 #ifdef CONFIG_PID_IN_CONTEXTIDR 53 static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd, 54 void *t) 55 { 56 u32 contextidr; 57 pid_t pid; 58 struct thread_info *thread = t; 59 60 if (cmd != THREAD_NOTIFY_SWITCH) 61 return NOTIFY_DONE; 62 63 pid = task_pid_nr(thread->task) << ASID_BITS; 64 asm volatile( 65 " mrc p15, 0, %0, c13, c0, 1\n" 66 " and %0, %0, %2\n" 67 " orr %0, %0, %1\n" 68 " mcr p15, 0, %0, c13, c0, 1\n" 69 : "=r" (contextidr), "+r" (pid) 70 : "I" (~ASID_MASK)); 71 isb(); 72 73 return NOTIFY_OK; 74 } 75 76 static struct notifier_block contextidr_notifier_block = { 77 .notifier_call = contextidr_notifier, 78 }; 79 80 static int __init contextidr_notifier_init(void) 81 { 82 return thread_register_notifier(&contextidr_notifier_block); 83 } 84 arch_initcall(contextidr_notifier_init); 85 #endif 86 87 /* 88 * We fork()ed a process, and we need a new context for the child 89 * to run in. 90 */ 91 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) 92 { 93 mm->context.id = 0; 94 raw_spin_lock_init(&mm->context.id_lock); 95 } 96 97 static void flush_context(void) 98 { 99 cpu_set_reserved_ttbr0(); 100 local_flush_tlb_all(); 101 if (icache_is_vivt_asid_tagged()) { 102 __flush_icache_all(); 103 dsb(); 104 } 105 } 106 107 #ifdef CONFIG_SMP 108 109 static void set_mm_context(struct mm_struct *mm, unsigned int asid) 110 { 111 unsigned long flags; 112 113 /* 114 * Locking needed for multi-threaded applications where the 115 * same mm->context.id could be set from different CPUs during 116 * the broadcast. This function is also called via IPI so the 117 * mm->context.id_lock has to be IRQ-safe. 118 */ 119 raw_spin_lock_irqsave(&mm->context.id_lock, flags); 120 if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) { 121 /* 122 * Old version of ASID found. Set the new one and 123 * reset mm_cpumask(mm). 124 */ 125 mm->context.id = asid; 126 cpumask_clear(mm_cpumask(mm)); 127 } 128 raw_spin_unlock_irqrestore(&mm->context.id_lock, flags); 129 130 /* 131 * Set the mm_cpumask(mm) bit for the current CPU. 132 */ 133 cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm)); 134 } 135 136 /* 137 * Reset the ASID on the current CPU. This function call is broadcast 138 * from the CPU handling the ASID rollover and holding cpu_asid_lock. 139 */ 140 static void reset_context(void *info) 141 { 142 unsigned int asid; 143 unsigned int cpu = smp_processor_id(); 144 struct mm_struct *mm = current->active_mm; 145 146 smp_rmb(); 147 asid = cpu_last_asid + cpu + 1; 148 149 flush_context(); 150 set_mm_context(mm, asid); 151 152 /* set the new ASID */ 153 cpu_switch_mm(mm->pgd, mm); 154 } 155 156 #else 157 158 static inline void set_mm_context(struct mm_struct *mm, unsigned int asid) 159 { 160 mm->context.id = asid; 161 cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id())); 162 } 163 164 #endif 165 166 void __new_context(struct mm_struct *mm) 167 { 168 unsigned int asid; 169 170 raw_spin_lock(&cpu_asid_lock); 171 #ifdef CONFIG_SMP 172 /* 173 * Check the ASID again, in case the change was broadcast from 174 * another CPU before we acquired the lock. 175 */ 176 if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) { 177 cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm)); 178 raw_spin_unlock(&cpu_asid_lock); 179 return; 180 } 181 #endif 182 /* 183 * At this point, it is guaranteed that the current mm (with 184 * an old ASID) isn't active on any other CPU since the ASIDs 185 * are changed simultaneously via IPI. 186 */ 187 asid = ++cpu_last_asid; 188 if (asid == 0) 189 asid = cpu_last_asid = ASID_FIRST_VERSION; 190 191 /* 192 * If we've used up all our ASIDs, we need 193 * to start a new version and flush the TLB. 194 */ 195 if (unlikely((asid & ~ASID_MASK) == 0)) { 196 asid = cpu_last_asid + smp_processor_id() + 1; 197 flush_context(); 198 #ifdef CONFIG_SMP 199 smp_wmb(); 200 smp_call_function(reset_context, NULL, 1); 201 #endif 202 cpu_last_asid += NR_CPUS; 203 } 204 205 set_mm_context(mm, asid); 206 raw_spin_unlock(&cpu_asid_lock); 207 } 208