1/* 2 * linux/arch/arm/mm/cache-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2005 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv7 processor support. 12 */ 13#include <linux/linkage.h> 14#include <linux/init.h> 15#include <asm/assembler.h> 16#include <asm/unwind.h> 17 18#include "proc-macros.S" 19 20/* 21 * v7_flush_dcache_all() 22 * 23 * Flush the whole D-cache. 24 * 25 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 26 * 27 * - mm - mm_struct describing address space 28 */ 29ENTRY(v7_flush_dcache_all) 30 dmb @ ensure ordering with previous memory accesses 31 mrc p15, 1, r0, c0, c0, 1 @ read clidr 32 ands r3, r0, #0x7000000 @ extract loc from clidr 33 mov r3, r3, lsr #23 @ left align loc bit field 34 beq finished @ if loc is 0, then no need to clean 35 mov r10, #0 @ start clean at cache level 0 36loop1: 37 add r2, r10, r10, lsr #1 @ work out 3x current cache level 38 mov r1, r0, lsr r2 @ extract cache type bits from clidr 39 and r1, r1, #7 @ mask of the bits for current cache only 40 cmp r1, #2 @ see what cache we have at this level 41 blt skip @ skip if no cache, or just i-cache 42 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 43 isb @ isb to sych the new cssr&csidr 44 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 45 and r2, r1, #7 @ extract the length of the cache lines 46 add r2, r2, #4 @ add 4 (line length offset) 47 ldr r4, =0x3ff 48 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 49 clz r5, r4 @ find bit position of way size increment 50 ldr r7, =0x7fff 51 ands r7, r7, r1, lsr #13 @ extract max number of the index size 52loop2: 53 mov r9, r4 @ create working copy of max way size 54loop3: 55 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 56 THUMB( lsl r6, r9, r5 ) 57 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 58 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 59 THUMB( lsl r6, r7, r2 ) 60 THUMB( orr r11, r11, r6 ) @ factor index number into r11 61 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 62 subs r9, r9, #1 @ decrement the way 63 bge loop3 64 subs r7, r7, #1 @ decrement the index 65 bge loop2 66skip: 67 add r10, r10, #2 @ increment cache number 68 cmp r3, r10 69 bgt loop1 70finished: 71 mov r10, #0 @ swith back to cache level 0 72 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 73 dsb 74 isb 75 mov pc, lr 76ENDPROC(v7_flush_dcache_all) 77 78/* 79 * v7_flush_cache_all() 80 * 81 * Flush the entire cache system. 82 * The data cache flush is now achieved using atomic clean / invalidates 83 * working outwards from L1 cache. This is done using Set/Way based cache 84 * maintainance instructions. 85 * The instruction cache can still be invalidated back to the point of 86 * unification in a single instruction. 87 * 88 */ 89ENTRY(v7_flush_kern_cache_all) 90 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 91 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 92 bl v7_flush_dcache_all 93 mov r0, #0 94#ifdef CONFIG_SMP 95 mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable 96#else 97 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 98#endif 99 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 100 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 101 mov pc, lr 102ENDPROC(v7_flush_kern_cache_all) 103 104/* 105 * v7_flush_cache_all() 106 * 107 * Flush all TLB entries in a particular address space 108 * 109 * - mm - mm_struct describing address space 110 */ 111ENTRY(v7_flush_user_cache_all) 112 /*FALLTHROUGH*/ 113 114/* 115 * v7_flush_cache_range(start, end, flags) 116 * 117 * Flush a range of TLB entries in the specified address space. 118 * 119 * - start - start address (may not be aligned) 120 * - end - end address (exclusive, may not be aligned) 121 * - flags - vm_area_struct flags describing address space 122 * 123 * It is assumed that: 124 * - we have a VIPT cache. 125 */ 126ENTRY(v7_flush_user_cache_range) 127 mov pc, lr 128ENDPROC(v7_flush_user_cache_all) 129ENDPROC(v7_flush_user_cache_range) 130 131/* 132 * v7_coherent_kern_range(start,end) 133 * 134 * Ensure that the I and D caches are coherent within specified 135 * region. This is typically used when code has been written to 136 * a memory region, and will be executed. 137 * 138 * - start - virtual start address of region 139 * - end - virtual end address of region 140 * 141 * It is assumed that: 142 * - the Icache does not read data from the write buffer 143 */ 144ENTRY(v7_coherent_kern_range) 145 /* FALLTHROUGH */ 146 147/* 148 * v7_coherent_user_range(start,end) 149 * 150 * Ensure that the I and D caches are coherent within specified 151 * region. This is typically used when code has been written to 152 * a memory region, and will be executed. 153 * 154 * - start - virtual start address of region 155 * - end - virtual end address of region 156 * 157 * It is assumed that: 158 * - the Icache does not read data from the write buffer 159 */ 160ENTRY(v7_coherent_user_range) 161 UNWIND(.fnstart ) 162 dcache_line_size r2, r3 163 sub r3, r2, #1 164 bic r0, r0, r3 1651: 166 USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification 167 dsb 168 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line 169 add r0, r0, r2 1702: 171 cmp r0, r1 172 blo 1b 173 mov r0, #0 174#ifdef CONFIG_SMP 175 mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable 176#else 177 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 178#endif 179 dsb 180 isb 181 mov pc, lr 182 183/* 184 * Fault handling for the cache operation above. If the virtual address in r0 185 * isn't mapped, just try the next page. 186 */ 1879001: 188 mov r0, r0, lsr #12 189 mov r0, r0, lsl #12 190 add r0, r0, #4096 191 b 2b 192 UNWIND(.fnend ) 193ENDPROC(v7_coherent_kern_range) 194ENDPROC(v7_coherent_user_range) 195 196/* 197 * v7_flush_kern_dcache_area(void *addr, size_t size) 198 * 199 * Ensure that the data held in the page kaddr is written back 200 * to the page in question. 201 * 202 * - addr - kernel address 203 * - size - region size 204 */ 205ENTRY(v7_flush_kern_dcache_area) 206 dcache_line_size r2, r3 207 add r1, r0, r1 2081: 209 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 210 add r0, r0, r2 211 cmp r0, r1 212 blo 1b 213 dsb 214 mov pc, lr 215ENDPROC(v7_flush_kern_dcache_area) 216 217/* 218 * v7_dma_inv_range(start,end) 219 * 220 * Invalidate the data cache within the specified region; we will 221 * be performing a DMA operation in this region and we want to 222 * purge old data in the cache. 223 * 224 * - start - virtual start address of region 225 * - end - virtual end address of region 226 */ 227v7_dma_inv_range: 228 dcache_line_size r2, r3 229 sub r3, r2, #1 230 tst r0, r3 231 bic r0, r0, r3 232 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 233 234 tst r1, r3 235 bic r1, r1, r3 236 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 2371: 238 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 239 add r0, r0, r2 240 cmp r0, r1 241 blo 1b 242 dsb 243 mov pc, lr 244ENDPROC(v7_dma_inv_range) 245 246/* 247 * v7_dma_clean_range(start,end) 248 * - start - virtual start address of region 249 * - end - virtual end address of region 250 */ 251v7_dma_clean_range: 252 dcache_line_size r2, r3 253 sub r3, r2, #1 254 bic r0, r0, r3 2551: 256 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 257 add r0, r0, r2 258 cmp r0, r1 259 blo 1b 260 dsb 261 mov pc, lr 262ENDPROC(v7_dma_clean_range) 263 264/* 265 * v7_dma_flush_range(start,end) 266 * - start - virtual start address of region 267 * - end - virtual end address of region 268 */ 269ENTRY(v7_dma_flush_range) 270 dcache_line_size r2, r3 271 sub r3, r2, #1 272 bic r0, r0, r3 2731: 274 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 275 add r0, r0, r2 276 cmp r0, r1 277 blo 1b 278 dsb 279 mov pc, lr 280ENDPROC(v7_dma_flush_range) 281 282/* 283 * dma_map_area(start, size, dir) 284 * - start - kernel virtual start address 285 * - size - size of region 286 * - dir - DMA direction 287 */ 288ENTRY(v7_dma_map_area) 289 add r1, r1, r0 290 teq r2, #DMA_FROM_DEVICE 291 beq v7_dma_inv_range 292 b v7_dma_clean_range 293ENDPROC(v7_dma_map_area) 294 295/* 296 * dma_unmap_area(start, size, dir) 297 * - start - kernel virtual start address 298 * - size - size of region 299 * - dir - DMA direction 300 */ 301ENTRY(v7_dma_unmap_area) 302 add r1, r1, r0 303 teq r2, #DMA_TO_DEVICE 304 bne v7_dma_inv_range 305 mov pc, lr 306ENDPROC(v7_dma_unmap_area) 307 308 __INITDATA 309 310 .type v7_cache_fns, #object 311ENTRY(v7_cache_fns) 312 .long v7_flush_kern_cache_all 313 .long v7_flush_user_cache_all 314 .long v7_flush_user_cache_range 315 .long v7_coherent_kern_range 316 .long v7_coherent_user_range 317 .long v7_flush_kern_dcache_area 318 .long v7_dma_map_area 319 .long v7_dma_unmap_area 320 .long v7_dma_flush_range 321 .size v7_cache_fns, . - v7_cache_fns 322