1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/mm/cache-v7.S 4 * 5 * Copyright (C) 2001 Deep Blue Solutions Ltd. 6 * Copyright (C) 2005 ARM Ltd. 7 * 8 * This is the "shell" of the ARMv7 processor support. 9 */ 10#include <linux/linkage.h> 11#include <linux/init.h> 12#include <asm/assembler.h> 13#include <asm/errno.h> 14#include <asm/unwind.h> 15#include <asm/hardware/cache-b15-rac.h> 16 17#include "proc-macros.S" 18 19/* 20 * The secondary kernel init calls v7_flush_dcache_all before it enables 21 * the L1; however, the L1 comes out of reset in an undefined state, so 22 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch 23 * of cache lines with uninitialized data and uninitialized tags to get 24 * written out to memory, which does really unpleasant things to the main 25 * processor. We fix this by performing an invalidate, rather than a 26 * clean + invalidate, before jumping into the kernel. 27 * 28 * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs 29 * to be called for both secondary cores startup and primary core resume 30 * procedures. 31 */ 32ENTRY(v7_invalidate_l1) 33 mov r0, #0 34 mcr p15, 2, r0, c0, c0, 0 35 mrc p15, 1, r0, c0, c0, 0 36 37 movw r1, #0x7fff 38 and r2, r1, r0, lsr #13 39 40 movw r1, #0x3ff 41 42 and r3, r1, r0, lsr #3 @ NumWays - 1 43 add r2, r2, #1 @ NumSets 44 45 and r0, r0, #0x7 46 add r0, r0, #4 @ SetShift 47 48 clz r1, r3 @ WayShift 49 add r4, r3, #1 @ NumWays 501: sub r2, r2, #1 @ NumSets-- 51 mov r3, r4 @ Temp = NumWays 522: subs r3, r3, #1 @ Temp-- 53 mov r5, r3, lsl r1 54 mov r6, r2, lsl r0 55 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) 56 mcr p15, 0, r5, c7, c6, 2 57 bgt 2b 58 cmp r2, #0 59 bgt 1b 60 dsb st 61 isb 62 ret lr 63ENDPROC(v7_invalidate_l1) 64 65/* 66 * v7_flush_icache_all() 67 * 68 * Flush the whole I-cache. 69 * 70 * Registers: 71 * r0 - set to 0 72 */ 73ENTRY(v7_flush_icache_all) 74 mov r0, #0 75 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 76 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 77 ret lr 78ENDPROC(v7_flush_icache_all) 79 80 /* 81 * v7_flush_dcache_louis() 82 * 83 * Flush the D-cache up to the Level of Unification Inner Shareable 84 * 85 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 86 */ 87 88ENTRY(v7_flush_dcache_louis) 89 dmb @ ensure ordering with previous memory accesses 90 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr 91ALT_SMP(mov r3, r0, lsr #20) @ move LoUIS into position 92ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position 93 ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr 94 bne start_flush_levels @ LoU != 0, start flushing 95#ifdef CONFIG_ARM_ERRATA_643719 96ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register 97ALT_UP( ret lr) @ LoUU is zero, so nothing to do 98 movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p? 99 movt r1, #:upper16:(0x410fc090 >> 4) 100 teq r1, r2, lsr #4 @ test for errata affected core and if so... 101 moveq r3, #1 << 1 @ fix LoUIS value 102 beq start_flush_levels @ start flushing cache levels 103#endif 104 ret lr 105ENDPROC(v7_flush_dcache_louis) 106 107/* 108 * v7_flush_dcache_all() 109 * 110 * Flush the whole D-cache. 111 * 112 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 113 * 114 * - mm - mm_struct describing address space 115 */ 116ENTRY(v7_flush_dcache_all) 117 dmb @ ensure ordering with previous memory accesses 118 mrc p15, 1, r0, c0, c0, 1 @ read clidr 119 mov r3, r0, lsr #23 @ move LoC into position 120 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr 121 beq finished @ if loc is 0, then no need to clean 122start_flush_levels: 123 mov r10, #0 @ start clean at cache level 0 124flush_levels: 125 add r2, r10, r10, lsr #1 @ work out 3x current cache level 126 mov r1, r0, lsr r2 @ extract cache type bits from clidr 127 and r1, r1, #7 @ mask of the bits for current cache only 128 cmp r1, #2 @ see what cache we have at this level 129 blt skip @ skip if no cache, or just i-cache 130#ifdef CONFIG_PREEMPT 131 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic 132#endif 133 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 134 isb @ isb to sych the new cssr&csidr 135 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 136#ifdef CONFIG_PREEMPT 137 restore_irqs_notrace r9 138#endif 139 and r2, r1, #7 @ extract the length of the cache lines 140 add r2, r2, #4 @ add 4 (line length offset) 141 movw r4, #0x3ff 142 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 143 clz r5, r4 @ find bit position of way size increment 144 movw r7, #0x7fff 145 ands r7, r7, r1, lsr #13 @ extract max number of the index size 146loop1: 147 mov r9, r7 @ create working copy of max index 148loop2: 149 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 150 THUMB( lsl r6, r4, r5 ) 151 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 152 ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 153 THUMB( lsl r6, r9, r2 ) 154 THUMB( orr r11, r11, r6 ) @ factor index number into r11 155 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 156 subs r9, r9, #1 @ decrement the index 157 bge loop2 158 subs r4, r4, #1 @ decrement the way 159 bge loop1 160skip: 161 add r10, r10, #2 @ increment cache number 162 cmp r3, r10 163 bgt flush_levels 164finished: 165 mov r10, #0 @ switch back to cache level 0 166 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 167 dsb st 168 isb 169 ret lr 170ENDPROC(v7_flush_dcache_all) 171 172/* 173 * v7_flush_cache_all() 174 * 175 * Flush the entire cache system. 176 * The data cache flush is now achieved using atomic clean / invalidates 177 * working outwards from L1 cache. This is done using Set/Way based cache 178 * maintenance instructions. 179 * The instruction cache can still be invalidated back to the point of 180 * unification in a single instruction. 181 * 182 */ 183ENTRY(v7_flush_kern_cache_all) 184 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 185 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 186 bl v7_flush_dcache_all 187 mov r0, #0 188 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 189 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 190 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 191 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 192 ret lr 193ENDPROC(v7_flush_kern_cache_all) 194 195 /* 196 * v7_flush_kern_cache_louis(void) 197 * 198 * Flush the data cache up to Level of Unification Inner Shareable. 199 * Invalidate the I-cache to the point of unification. 200 */ 201ENTRY(v7_flush_kern_cache_louis) 202 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 203 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 204 bl v7_flush_dcache_louis 205 mov r0, #0 206 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 207 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 208 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 209 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 210 ret lr 211ENDPROC(v7_flush_kern_cache_louis) 212 213/* 214 * v7_flush_cache_all() 215 * 216 * Flush all TLB entries in a particular address space 217 * 218 * - mm - mm_struct describing address space 219 */ 220ENTRY(v7_flush_user_cache_all) 221 /*FALLTHROUGH*/ 222 223/* 224 * v7_flush_cache_range(start, end, flags) 225 * 226 * Flush a range of TLB entries in the specified address space. 227 * 228 * - start - start address (may not be aligned) 229 * - end - end address (exclusive, may not be aligned) 230 * - flags - vm_area_struct flags describing address space 231 * 232 * It is assumed that: 233 * - we have a VIPT cache. 234 */ 235ENTRY(v7_flush_user_cache_range) 236 ret lr 237ENDPROC(v7_flush_user_cache_all) 238ENDPROC(v7_flush_user_cache_range) 239 240/* 241 * v7_coherent_kern_range(start,end) 242 * 243 * Ensure that the I and D caches are coherent within specified 244 * region. This is typically used when code has been written to 245 * a memory region, and will be executed. 246 * 247 * - start - virtual start address of region 248 * - end - virtual end address of region 249 * 250 * It is assumed that: 251 * - the Icache does not read data from the write buffer 252 */ 253ENTRY(v7_coherent_kern_range) 254 /* FALLTHROUGH */ 255 256/* 257 * v7_coherent_user_range(start,end) 258 * 259 * Ensure that the I and D caches are coherent within specified 260 * region. This is typically used when code has been written to 261 * a memory region, and will be executed. 262 * 263 * - start - virtual start address of region 264 * - end - virtual end address of region 265 * 266 * It is assumed that: 267 * - the Icache does not read data from the write buffer 268 */ 269ENTRY(v7_coherent_user_range) 270 UNWIND(.fnstart ) 271 dcache_line_size r2, r3 272 sub r3, r2, #1 273 bic r12, r0, r3 274#ifdef CONFIG_ARM_ERRATA_764369 275 ALT_SMP(W(dsb)) 276 ALT_UP(W(nop)) 277#endif 2781: 279 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification 280 add r12, r12, r2 281 cmp r12, r1 282 blo 1b 283 dsb ishst 284 icache_line_size r2, r3 285 sub r3, r2, #1 286 bic r12, r0, r3 2872: 288 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line 289 add r12, r12, r2 290 cmp r12, r1 291 blo 2b 292 mov r0, #0 293 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 294 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB 295 dsb ishst 296 isb 297 ret lr 298 299/* 300 * Fault handling for the cache operation above. If the virtual address in r0 301 * isn't mapped, fail with -EFAULT. 302 */ 3039001: 304#ifdef CONFIG_ARM_ERRATA_775420 305 dsb 306#endif 307 mov r0, #-EFAULT 308 ret lr 309 UNWIND(.fnend ) 310ENDPROC(v7_coherent_kern_range) 311ENDPROC(v7_coherent_user_range) 312 313/* 314 * v7_flush_kern_dcache_area(void *addr, size_t size) 315 * 316 * Ensure that the data held in the page kaddr is written back 317 * to the page in question. 318 * 319 * - addr - kernel address 320 * - size - region size 321 */ 322ENTRY(v7_flush_kern_dcache_area) 323 dcache_line_size r2, r3 324 add r1, r0, r1 325 sub r3, r2, #1 326 bic r0, r0, r3 327#ifdef CONFIG_ARM_ERRATA_764369 328 ALT_SMP(W(dsb)) 329 ALT_UP(W(nop)) 330#endif 3311: 332 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 333 add r0, r0, r2 334 cmp r0, r1 335 blo 1b 336 dsb st 337 ret lr 338ENDPROC(v7_flush_kern_dcache_area) 339 340/* 341 * v7_dma_inv_range(start,end) 342 * 343 * Invalidate the data cache within the specified region; we will 344 * be performing a DMA operation in this region and we want to 345 * purge old data in the cache. 346 * 347 * - start - virtual start address of region 348 * - end - virtual end address of region 349 */ 350v7_dma_inv_range: 351 dcache_line_size r2, r3 352 sub r3, r2, #1 353 tst r0, r3 354 bic r0, r0, r3 355#ifdef CONFIG_ARM_ERRATA_764369 356 ALT_SMP(W(dsb)) 357 ALT_UP(W(nop)) 358#endif 359 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 360 addne r0, r0, r2 361 362 tst r1, r3 363 bic r1, r1, r3 364 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 365 cmp r0, r1 3661: 367 mcrlo p15, 0, r0, c7, c6, 1 @ invalidate D / U line 368 addlo r0, r0, r2 369 cmplo r0, r1 370 blo 1b 371 dsb st 372 ret lr 373ENDPROC(v7_dma_inv_range) 374 375/* 376 * v7_dma_clean_range(start,end) 377 * - start - virtual start address of region 378 * - end - virtual end address of region 379 */ 380v7_dma_clean_range: 381 dcache_line_size r2, r3 382 sub r3, r2, #1 383 bic r0, r0, r3 384#ifdef CONFIG_ARM_ERRATA_764369 385 ALT_SMP(W(dsb)) 386 ALT_UP(W(nop)) 387#endif 3881: 389 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 390 add r0, r0, r2 391 cmp r0, r1 392 blo 1b 393 dsb st 394 ret lr 395ENDPROC(v7_dma_clean_range) 396 397/* 398 * v7_dma_flush_range(start,end) 399 * - start - virtual start address of region 400 * - end - virtual end address of region 401 */ 402ENTRY(v7_dma_flush_range) 403 dcache_line_size r2, r3 404 sub r3, r2, #1 405 bic r0, r0, r3 406#ifdef CONFIG_ARM_ERRATA_764369 407 ALT_SMP(W(dsb)) 408 ALT_UP(W(nop)) 409#endif 4101: 411 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 412 add r0, r0, r2 413 cmp r0, r1 414 blo 1b 415 dsb st 416 ret lr 417ENDPROC(v7_dma_flush_range) 418 419/* 420 * dma_map_area(start, size, dir) 421 * - start - kernel virtual start address 422 * - size - size of region 423 * - dir - DMA direction 424 */ 425ENTRY(v7_dma_map_area) 426 add r1, r1, r0 427 teq r2, #DMA_FROM_DEVICE 428 beq v7_dma_inv_range 429 b v7_dma_clean_range 430ENDPROC(v7_dma_map_area) 431 432/* 433 * dma_unmap_area(start, size, dir) 434 * - start - kernel virtual start address 435 * - size - size of region 436 * - dir - DMA direction 437 */ 438ENTRY(v7_dma_unmap_area) 439 add r1, r1, r0 440 teq r2, #DMA_TO_DEVICE 441 bne v7_dma_inv_range 442 ret lr 443ENDPROC(v7_dma_unmap_area) 444 445 __INITDATA 446 447 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 448 define_cache_functions v7 449 450 /* The Broadcom Brahma-B15 read-ahead cache requires some modifications 451 * to the v7_cache_fns, we only override the ones we need 452 */ 453#ifndef CONFIG_CACHE_B15_RAC 454 globl_equ b15_flush_kern_cache_all, v7_flush_kern_cache_all 455#endif 456 globl_equ b15_flush_icache_all, v7_flush_icache_all 457 globl_equ b15_flush_kern_cache_louis, v7_flush_kern_cache_louis 458 globl_equ b15_flush_user_cache_all, v7_flush_user_cache_all 459 globl_equ b15_flush_user_cache_range, v7_flush_user_cache_range 460 globl_equ b15_coherent_kern_range, v7_coherent_kern_range 461 globl_equ b15_coherent_user_range, v7_coherent_user_range 462 globl_equ b15_flush_kern_dcache_area, v7_flush_kern_dcache_area 463 464 globl_equ b15_dma_map_area, v7_dma_map_area 465 globl_equ b15_dma_unmap_area, v7_dma_unmap_area 466 globl_equ b15_dma_flush_range, v7_dma_flush_range 467 468 define_cache_functions b15 469