1/* 2 * linux/arch/arm/mm/cache-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2005 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv7 processor support. 12 */ 13#include <linux/linkage.h> 14#include <linux/init.h> 15#include <asm/assembler.h> 16#include <asm/errno.h> 17#include <asm/unwind.h> 18 19#include "proc-macros.S" 20 21/* 22 * v7_flush_icache_all() 23 * 24 * Flush the whole I-cache. 25 * 26 * Registers: 27 * r0 - set to 0 28 */ 29ENTRY(v7_flush_icache_all) 30 mov r0, #0 31 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 32 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 33 mov pc, lr 34ENDPROC(v7_flush_icache_all) 35 36 /* 37 * v7_flush_dcache_louis() 38 * 39 * Flush the D-cache up to the Level of Unification Inner Shareable 40 * 41 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 42 */ 43 44ENTRY(v7_flush_dcache_louis) 45 dmb @ ensure ordering with previous memory accesses 46 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr 47 ands r3, r0, #0xe00000 @ extract LoUIS from clidr 48 mov r3, r3, lsr #20 @ r3 = LoUIS * 2 49 moveq pc, lr @ return if level == 0 50 mov r10, #0 @ r10 (starting level) = 0 51 b flush_levels @ start flushing cache levels 52ENDPROC(v7_flush_dcache_louis) 53 54/* 55 * v7_flush_dcache_all() 56 * 57 * Flush the whole D-cache. 58 * 59 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 60 * 61 * - mm - mm_struct describing address space 62 */ 63ENTRY(v7_flush_dcache_all) 64 dmb @ ensure ordering with previous memory accesses 65 mrc p15, 1, r0, c0, c0, 1 @ read clidr 66 ands r3, r0, #0x7000000 @ extract loc from clidr 67 mov r3, r3, lsr #23 @ left align loc bit field 68 beq finished @ if loc is 0, then no need to clean 69 mov r10, #0 @ start clean at cache level 0 70flush_levels: 71 add r2, r10, r10, lsr #1 @ work out 3x current cache level 72 mov r1, r0, lsr r2 @ extract cache type bits from clidr 73 and r1, r1, #7 @ mask of the bits for current cache only 74 cmp r1, #2 @ see what cache we have at this level 75 blt skip @ skip if no cache, or just i-cache 76#ifdef CONFIG_PREEMPT 77 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic 78#endif 79 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 80 isb @ isb to sych the new cssr&csidr 81 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 82#ifdef CONFIG_PREEMPT 83 restore_irqs_notrace r9 84#endif 85 and r2, r1, #7 @ extract the length of the cache lines 86 add r2, r2, #4 @ add 4 (line length offset) 87 ldr r4, =0x3ff 88 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 89 clz r5, r4 @ find bit position of way size increment 90 ldr r7, =0x7fff 91 ands r7, r7, r1, lsr #13 @ extract max number of the index size 92loop1: 93 mov r9, r4 @ create working copy of max way size 94loop2: 95 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 96 THUMB( lsl r6, r9, r5 ) 97 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 98 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 99 THUMB( lsl r6, r7, r2 ) 100 THUMB( orr r11, r11, r6 ) @ factor index number into r11 101 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 102 subs r9, r9, #1 @ decrement the way 103 bge loop2 104 subs r7, r7, #1 @ decrement the index 105 bge loop1 106skip: 107 add r10, r10, #2 @ increment cache number 108 cmp r3, r10 109 bgt flush_levels 110finished: 111 mov r10, #0 @ swith back to cache level 0 112 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 113 dsb 114 isb 115 mov pc, lr 116ENDPROC(v7_flush_dcache_all) 117 118/* 119 * v7_flush_cache_all() 120 * 121 * Flush the entire cache system. 122 * The data cache flush is now achieved using atomic clean / invalidates 123 * working outwards from L1 cache. This is done using Set/Way based cache 124 * maintenance instructions. 125 * The instruction cache can still be invalidated back to the point of 126 * unification in a single instruction. 127 * 128 */ 129ENTRY(v7_flush_kern_cache_all) 130 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 131 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 132 bl v7_flush_dcache_all 133 mov r0, #0 134 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 135 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 136 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 137 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 138 mov pc, lr 139ENDPROC(v7_flush_kern_cache_all) 140 141 /* 142 * v7_flush_kern_cache_louis(void) 143 * 144 * Flush the data cache up to Level of Unification Inner Shareable. 145 * Invalidate the I-cache to the point of unification. 146 */ 147ENTRY(v7_flush_kern_cache_louis) 148 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 149 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 150 bl v7_flush_dcache_louis 151 mov r0, #0 152 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 153 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 154 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 155 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 156 mov pc, lr 157ENDPROC(v7_flush_kern_cache_louis) 158 159/* 160 * v7_flush_cache_all() 161 * 162 * Flush all TLB entries in a particular address space 163 * 164 * - mm - mm_struct describing address space 165 */ 166ENTRY(v7_flush_user_cache_all) 167 /*FALLTHROUGH*/ 168 169/* 170 * v7_flush_cache_range(start, end, flags) 171 * 172 * Flush a range of TLB entries in the specified address space. 173 * 174 * - start - start address (may not be aligned) 175 * - end - end address (exclusive, may not be aligned) 176 * - flags - vm_area_struct flags describing address space 177 * 178 * It is assumed that: 179 * - we have a VIPT cache. 180 */ 181ENTRY(v7_flush_user_cache_range) 182 mov pc, lr 183ENDPROC(v7_flush_user_cache_all) 184ENDPROC(v7_flush_user_cache_range) 185 186/* 187 * v7_coherent_kern_range(start,end) 188 * 189 * Ensure that the I and D caches are coherent within specified 190 * region. This is typically used when code has been written to 191 * a memory region, and will be executed. 192 * 193 * - start - virtual start address of region 194 * - end - virtual end address of region 195 * 196 * It is assumed that: 197 * - the Icache does not read data from the write buffer 198 */ 199ENTRY(v7_coherent_kern_range) 200 /* FALLTHROUGH */ 201 202/* 203 * v7_coherent_user_range(start,end) 204 * 205 * Ensure that the I and D caches are coherent within specified 206 * region. This is typically used when code has been written to 207 * a memory region, and will be executed. 208 * 209 * - start - virtual start address of region 210 * - end - virtual end address of region 211 * 212 * It is assumed that: 213 * - the Icache does not read data from the write buffer 214 */ 215ENTRY(v7_coherent_user_range) 216 UNWIND(.fnstart ) 217 dcache_line_size r2, r3 218 sub r3, r2, #1 219 bic r12, r0, r3 220#ifdef CONFIG_ARM_ERRATA_764369 221 ALT_SMP(W(dsb)) 222 ALT_UP(W(nop)) 223#endif 2241: 225 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification 226 add r12, r12, r2 227 cmp r12, r1 228 blo 1b 229 dsb 230 icache_line_size r2, r3 231 sub r3, r2, #1 232 bic r12, r0, r3 2332: 234 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line 235 add r12, r12, r2 236 cmp r12, r1 237 blo 2b 238 mov r0, #0 239 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 240 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB 241 dsb 242 isb 243 mov pc, lr 244 245/* 246 * Fault handling for the cache operation above. If the virtual address in r0 247 * isn't mapped, fail with -EFAULT. 248 */ 2499001: 250#ifdef CONFIG_ARM_ERRATA_775420 251 dsb 252#endif 253 mov r0, #-EFAULT 254 mov pc, lr 255 UNWIND(.fnend ) 256ENDPROC(v7_coherent_kern_range) 257ENDPROC(v7_coherent_user_range) 258 259/* 260 * v7_flush_kern_dcache_area(void *addr, size_t size) 261 * 262 * Ensure that the data held in the page kaddr is written back 263 * to the page in question. 264 * 265 * - addr - kernel address 266 * - size - region size 267 */ 268ENTRY(v7_flush_kern_dcache_area) 269 dcache_line_size r2, r3 270 add r1, r0, r1 271 sub r3, r2, #1 272 bic r0, r0, r3 273#ifdef CONFIG_ARM_ERRATA_764369 274 ALT_SMP(W(dsb)) 275 ALT_UP(W(nop)) 276#endif 2771: 278 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 279 add r0, r0, r2 280 cmp r0, r1 281 blo 1b 282 dsb 283 mov pc, lr 284ENDPROC(v7_flush_kern_dcache_area) 285 286/* 287 * v7_dma_inv_range(start,end) 288 * 289 * Invalidate the data cache within the specified region; we will 290 * be performing a DMA operation in this region and we want to 291 * purge old data in the cache. 292 * 293 * - start - virtual start address of region 294 * - end - virtual end address of region 295 */ 296v7_dma_inv_range: 297 dcache_line_size r2, r3 298 sub r3, r2, #1 299 tst r0, r3 300 bic r0, r0, r3 301#ifdef CONFIG_ARM_ERRATA_764369 302 ALT_SMP(W(dsb)) 303 ALT_UP(W(nop)) 304#endif 305 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 306 307 tst r1, r3 308 bic r1, r1, r3 309 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 3101: 311 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 312 add r0, r0, r2 313 cmp r0, r1 314 blo 1b 315 dsb 316 mov pc, lr 317ENDPROC(v7_dma_inv_range) 318 319/* 320 * v7_dma_clean_range(start,end) 321 * - start - virtual start address of region 322 * - end - virtual end address of region 323 */ 324v7_dma_clean_range: 325 dcache_line_size r2, r3 326 sub r3, r2, #1 327 bic r0, r0, r3 328#ifdef CONFIG_ARM_ERRATA_764369 329 ALT_SMP(W(dsb)) 330 ALT_UP(W(nop)) 331#endif 3321: 333 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 334 add r0, r0, r2 335 cmp r0, r1 336 blo 1b 337 dsb 338 mov pc, lr 339ENDPROC(v7_dma_clean_range) 340 341/* 342 * v7_dma_flush_range(start,end) 343 * - start - virtual start address of region 344 * - end - virtual end address of region 345 */ 346ENTRY(v7_dma_flush_range) 347 dcache_line_size r2, r3 348 sub r3, r2, #1 349 bic r0, r0, r3 350#ifdef CONFIG_ARM_ERRATA_764369 351 ALT_SMP(W(dsb)) 352 ALT_UP(W(nop)) 353#endif 3541: 355 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 356 add r0, r0, r2 357 cmp r0, r1 358 blo 1b 359 dsb 360 mov pc, lr 361ENDPROC(v7_dma_flush_range) 362 363/* 364 * dma_map_area(start, size, dir) 365 * - start - kernel virtual start address 366 * - size - size of region 367 * - dir - DMA direction 368 */ 369ENTRY(v7_dma_map_area) 370 add r1, r1, r0 371 teq r2, #DMA_FROM_DEVICE 372 beq v7_dma_inv_range 373 b v7_dma_clean_range 374ENDPROC(v7_dma_map_area) 375 376/* 377 * dma_unmap_area(start, size, dir) 378 * - start - kernel virtual start address 379 * - size - size of region 380 * - dir - DMA direction 381 */ 382ENTRY(v7_dma_unmap_area) 383 add r1, r1, r0 384 teq r2, #DMA_TO_DEVICE 385 bne v7_dma_inv_range 386 mov pc, lr 387ENDPROC(v7_dma_unmap_area) 388 389 __INITDATA 390 391 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 392 define_cache_functions v7 393