1/* 2 * linux/arch/arm/mm/cache-v4wb.S 3 * 4 * Copyright (C) 1997-2002 Russell king 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10#include <linux/config.h> 11#include <linux/linkage.h> 12#include <linux/init.h> 13#include <asm/memory.h> 14#include <asm/page.h> 15#include "proc-macros.S" 16 17/* 18 * The size of one data cache line. 19 */ 20#define CACHE_DLINESIZE 32 21 22/* 23 * The total size of the data cache. 24 */ 25#if defined(CONFIG_CPU_SA110) 26# define CACHE_DSIZE 16384 27#elif defined(CONFIG_CPU_SA1100) 28# define CACHE_DSIZE 8192 29#else 30# error Unknown cache size 31#endif 32 33/* 34 * This is the size at which it becomes more efficient to 35 * clean the whole cache, rather than using the individual 36 * cache line maintainence instructions. 37 * 38 * Size Clean (ticks) Dirty (ticks) 39 * 4096 21 20 21 53 55 54 40 * 8192 40 41 40 106 100 102 41 * 16384 77 77 76 140 140 138 42 * 32768 150 149 150 214 216 212 <--- 43 * 65536 296 297 296 351 358 361 44 * 131072 591 591 591 656 657 651 45 * Whole 132 136 132 221 217 207 <--- 46 */ 47#define CACHE_DLIMIT (CACHE_DSIZE * 4) 48 49 .data 50flush_base: 51 .long FLUSH_BASE 52 .text 53 54/* 55 * flush_user_cache_all() 56 * 57 * Clean and invalidate all cache entries in a particular address 58 * space. 59 */ 60ENTRY(v4wb_flush_user_cache_all) 61 /* FALLTHROUGH */ 62/* 63 * flush_kern_cache_all() 64 * 65 * Clean and invalidate the entire cache. 66 */ 67ENTRY(v4wb_flush_kern_cache_all) 68 mov ip, #0 69 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 70__flush_whole_cache: 71 ldr r3, =flush_base 72 ldr r1, [r3, #0] 73 eor r1, r1, #CACHE_DSIZE 74 str r1, [r3, #0] 75 add r2, r1, #CACHE_DSIZE 761: ldr r3, [r1], #32 77 cmp r1, r2 78 blo 1b 79#ifdef FLUSH_BASE_MINICACHE 80 add r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE 81 sub r1, r2, #512 @ only 512 bytes 821: ldr r3, [r1], #32 83 cmp r1, r2 84 blo 1b 85#endif 86 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 87 mov pc, lr 88 89/* 90 * flush_user_cache_range(start, end, flags) 91 * 92 * Invalidate a range of cache entries in the specified 93 * address space. 94 * 95 * - start - start address (inclusive, page aligned) 96 * - end - end address (exclusive, page aligned) 97 * - flags - vma_area_struct flags describing address space 98 */ 99ENTRY(v4wb_flush_user_cache_range) 100 mov ip, #0 101 sub r3, r1, r0 @ calculate total size 102 tst r2, #VM_EXEC @ executable region? 103 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 104 105 cmp r3, #CACHE_DLIMIT @ total size >= limit? 106 bhs __flush_whole_cache @ flush whole D cache 107 1081: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 109 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 110 add r0, r0, #CACHE_DLINESIZE 111 cmp r0, r1 112 blo 1b 113 tst r2, #VM_EXEC 114 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 115 mov pc, lr 116 117/* 118 * flush_kern_dcache_page(void *page) 119 * 120 * Ensure no D cache aliasing occurs, either with itself or 121 * the I cache 122 * 123 * - addr - page aligned address 124 */ 125ENTRY(v4wb_flush_kern_dcache_page) 126 add r1, r0, #PAGE_SZ 127 /* fall through */ 128 129/* 130 * coherent_kern_range(start, end) 131 * 132 * Ensure coherency between the Icache and the Dcache in the 133 * region described by start. If you have non-snooping 134 * Harvard caches, you need to implement this function. 135 * 136 * - start - virtual start address 137 * - end - virtual end address 138 */ 139ENTRY(v4wb_coherent_kern_range) 140 /* fall through */ 141 142/* 143 * coherent_user_range(start, end) 144 * 145 * Ensure coherency between the Icache and the Dcache in the 146 * region described by start. If you have non-snooping 147 * Harvard caches, you need to implement this function. 148 * 149 * - start - virtual start address 150 * - end - virtual end address 151 */ 152ENTRY(v4wb_coherent_user_range) 153 bic r0, r0, #CACHE_DLINESIZE - 1 1541: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 155 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 156 add r0, r0, #CACHE_DLINESIZE 157 cmp r0, r1 158 blo 1b 159 mov ip, #0 160 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 161 mcr p15, 0, ip, c7, c10, 4 @ drain WB 162 mov pc, lr 163 164 165/* 166 * dma_inv_range(start, end) 167 * 168 * Invalidate (discard) the specified virtual address range. 169 * May not write back any entries. If 'start' or 'end' 170 * are not cache line aligned, those lines must be written 171 * back. 172 * 173 * - start - virtual start address 174 * - end - virtual end address 175 */ 176ENTRY(v4wb_dma_inv_range) 177 tst r0, #CACHE_DLINESIZE - 1 178 bic r0, r0, #CACHE_DLINESIZE - 1 179 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 180 tst r1, #CACHE_DLINESIZE - 1 181 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 1821: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 183 add r0, r0, #CACHE_DLINESIZE 184 cmp r0, r1 185 blo 1b 186 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 187 mov pc, lr 188 189/* 190 * dma_clean_range(start, end) 191 * 192 * Clean (write back) the specified virtual address range. 193 * 194 * - start - virtual start address 195 * - end - virtual end address 196 */ 197ENTRY(v4wb_dma_clean_range) 198 bic r0, r0, #CACHE_DLINESIZE - 1 1991: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 200 add r0, r0, #CACHE_DLINESIZE 201 cmp r0, r1 202 blo 1b 203 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 204 mov pc, lr 205 206/* 207 * dma_flush_range(start, end) 208 * 209 * Clean and invalidate the specified virtual address range. 210 * 211 * - start - virtual start address 212 * - end - virtual end address 213 * 214 * This is actually the same as v4wb_coherent_kern_range() 215 */ 216 .globl v4wb_dma_flush_range 217 .set v4wb_dma_flush_range, v4wb_coherent_kern_range 218 219 __INITDATA 220 221 .type v4wb_cache_fns, #object 222ENTRY(v4wb_cache_fns) 223 .long v4wb_flush_kern_cache_all 224 .long v4wb_flush_user_cache_all 225 .long v4wb_flush_user_cache_range 226 .long v4wb_coherent_kern_range 227 .long v4wb_coherent_user_range 228 .long v4wb_flush_kern_dcache_page 229 .long v4wb_dma_inv_range 230 .long v4wb_dma_clean_range 231 .long v4wb_dma_flush_range 232 .size v4wb_cache_fns, . - v4wb_cache_fns 233