1*4d3f18bbSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2e68f31f4SSebastian Hesselbarth /* 3e68f31f4SSebastian Hesselbarth * Marvell Tauros3 cache controller includes 4e68f31f4SSebastian Hesselbarth * 5e68f31f4SSebastian Hesselbarth * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 6e68f31f4SSebastian Hesselbarth * 7e68f31f4SSebastian Hesselbarth * based on GPL'ed 2.6 kernel sources 8e68f31f4SSebastian Hesselbarth * (c) Marvell International Ltd. 9e68f31f4SSebastian Hesselbarth */ 10e68f31f4SSebastian Hesselbarth 11e68f31f4SSebastian Hesselbarth #ifndef __ASM_ARM_HARDWARE_TAUROS3_H 12e68f31f4SSebastian Hesselbarth #define __ASM_ARM_HARDWARE_TAUROS3_H 13e68f31f4SSebastian Hesselbarth 14e68f31f4SSebastian Hesselbarth /* 15e68f31f4SSebastian Hesselbarth * Marvell Tauros3 L2CC is compatible with PL310 r0p0 16e68f31f4SSebastian Hesselbarth * but with PREFETCH_CTRL (r2p0) and an additional event counter. 17e68f31f4SSebastian Hesselbarth * Also, there is AUX2_CTRL for some Marvell specific control. 18e68f31f4SSebastian Hesselbarth */ 19e68f31f4SSebastian Hesselbarth 20e68f31f4SSebastian Hesselbarth #define TAUROS3_EVENT_CNT2_CFG 0x224 21e68f31f4SSebastian Hesselbarth #define TAUROS3_EVENT_CNT2_VAL 0x228 22e68f31f4SSebastian Hesselbarth #define TAUROS3_INV_ALL 0x780 23e68f31f4SSebastian Hesselbarth #define TAUROS3_CLEAN_ALL 0x784 24e68f31f4SSebastian Hesselbarth #define TAUROS3_AUX2_CTRL 0x820 25e68f31f4SSebastian Hesselbarth 26e68f31f4SSebastian Hesselbarth /* Registers shifts and masks */ 27e68f31f4SSebastian Hesselbarth #define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN (1 << 2) 28e68f31f4SSebastian Hesselbarth 29e68f31f4SSebastian Hesselbarth #endif 30