1 /* 2 * linux/arch/arm/mm/alignment.c 3 * 4 * Copyright (C) 1995 Linus Torvalds 5 * Modifications for ARM processor (c) 1995-2001 Russell King 6 * Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc. 7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. 8 * Copyright (C) 1996, Cygnus Software Technologies Ltd. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/config.h> 15 #include <linux/compiler.h> 16 #include <linux/kernel.h> 17 #include <linux/errno.h> 18 #include <linux/string.h> 19 #include <linux/ptrace.h> 20 #include <linux/proc_fs.h> 21 #include <linux/init.h> 22 23 #include <asm/uaccess.h> 24 #include <asm/unaligned.h> 25 26 #include "fault.h" 27 28 /* 29 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998 30 * /proc/sys/debug/alignment, modified and integrated into 31 * Linux 2.1 by Russell King 32 * 33 * Speed optimisations and better fault handling by Russell King. 34 * 35 * *** NOTE *** 36 * This code is not portable to processors with late data abort handling. 37 */ 38 #define CODING_BITS(i) (i & 0x0e000000) 39 40 #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */ 41 #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */ 42 #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */ 43 #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */ 44 #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */ 45 46 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0) 47 48 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */ 49 #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */ 50 51 #define RN_BITS(i) ((i >> 16) & 15) /* Rn */ 52 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */ 53 #define RM_BITS(i) (i & 15) /* Rm */ 54 55 #define REGMASK_BITS(i) (i & 0xffff) 56 #define OFFSET_BITS(i) (i & 0x0fff) 57 58 #define IS_SHIFT(i) (i & 0x0ff0) 59 #define SHIFT_BITS(i) ((i >> 7) & 0x1f) 60 #define SHIFT_TYPE(i) (i & 0x60) 61 #define SHIFT_LSL 0x00 62 #define SHIFT_LSR 0x20 63 #define SHIFT_ASR 0x40 64 #define SHIFT_RORRRX 0x60 65 66 static unsigned long ai_user; 67 static unsigned long ai_sys; 68 static unsigned long ai_skipped; 69 static unsigned long ai_half; 70 static unsigned long ai_word; 71 static unsigned long ai_dword; 72 static unsigned long ai_multi; 73 static int ai_usermode; 74 75 #ifdef CONFIG_PROC_FS 76 static const char *usermode_action[] = { 77 "ignored", 78 "warn", 79 "fixup", 80 "fixup+warn", 81 "signal", 82 "signal+warn" 83 }; 84 85 static int 86 proc_alignment_read(char *page, char **start, off_t off, int count, int *eof, 87 void *data) 88 { 89 char *p = page; 90 int len; 91 92 p += sprintf(p, "User:\t\t%lu\n", ai_user); 93 p += sprintf(p, "System:\t\t%lu\n", ai_sys); 94 p += sprintf(p, "Skipped:\t%lu\n", ai_skipped); 95 p += sprintf(p, "Half:\t\t%lu\n", ai_half); 96 p += sprintf(p, "Word:\t\t%lu\n", ai_word); 97 if (cpu_architecture() >= CPU_ARCH_ARMv5TE) 98 p += sprintf(p, "DWord:\t\t%lu\n", ai_dword); 99 p += sprintf(p, "Multi:\t\t%lu\n", ai_multi); 100 p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode, 101 usermode_action[ai_usermode]); 102 103 len = (p - page) - off; 104 if (len < 0) 105 len = 0; 106 107 *eof = (len <= count) ? 1 : 0; 108 *start = page + off; 109 110 return len; 111 } 112 113 static int proc_alignment_write(struct file *file, const char __user *buffer, 114 unsigned long count, void *data) 115 { 116 char mode; 117 118 if (count > 0) { 119 if (get_user(mode, buffer)) 120 return -EFAULT; 121 if (mode >= '0' && mode <= '5') 122 ai_usermode = mode - '0'; 123 } 124 return count; 125 } 126 127 #endif /* CONFIG_PROC_FS */ 128 129 union offset_union { 130 unsigned long un; 131 signed long sn; 132 }; 133 134 #define TYPE_ERROR 0 135 #define TYPE_FAULT 1 136 #define TYPE_LDST 2 137 #define TYPE_DONE 3 138 139 #ifdef __ARMEB__ 140 #define BE 1 141 #define FIRST_BYTE_16 "mov %1, %1, ror #8\n" 142 #define FIRST_BYTE_32 "mov %1, %1, ror #24\n" 143 #define NEXT_BYTE "ror #24" 144 #else 145 #define BE 0 146 #define FIRST_BYTE_16 147 #define FIRST_BYTE_32 148 #define NEXT_BYTE "lsr #8" 149 #endif 150 151 #define __get8_unaligned_check(ins,val,addr,err) \ 152 __asm__( \ 153 "1: "ins" %1, [%2], #1\n" \ 154 "2:\n" \ 155 " .section .fixup,\"ax\"\n" \ 156 " .align 2\n" \ 157 "3: mov %0, #1\n" \ 158 " b 2b\n" \ 159 " .previous\n" \ 160 " .section __ex_table,\"a\"\n" \ 161 " .align 3\n" \ 162 " .long 1b, 3b\n" \ 163 " .previous\n" \ 164 : "=r" (err), "=&r" (val), "=r" (addr) \ 165 : "0" (err), "2" (addr)) 166 167 #define __get16_unaligned_check(ins,val,addr) \ 168 do { \ 169 unsigned int err = 0, v, a = addr; \ 170 __get8_unaligned_check(ins,v,a,err); \ 171 val = v << ((BE) ? 8 : 0); \ 172 __get8_unaligned_check(ins,v,a,err); \ 173 val |= v << ((BE) ? 0 : 8); \ 174 if (err) \ 175 goto fault; \ 176 } while (0) 177 178 #define get16_unaligned_check(val,addr) \ 179 __get16_unaligned_check("ldrb",val,addr) 180 181 #define get16t_unaligned_check(val,addr) \ 182 __get16_unaligned_check("ldrbt",val,addr) 183 184 #define __get32_unaligned_check(ins,val,addr) \ 185 do { \ 186 unsigned int err = 0, v, a = addr; \ 187 __get8_unaligned_check(ins,v,a,err); \ 188 val = v << ((BE) ? 24 : 0); \ 189 __get8_unaligned_check(ins,v,a,err); \ 190 val |= v << ((BE) ? 16 : 8); \ 191 __get8_unaligned_check(ins,v,a,err); \ 192 val |= v << ((BE) ? 8 : 16); \ 193 __get8_unaligned_check(ins,v,a,err); \ 194 val |= v << ((BE) ? 0 : 24); \ 195 if (err) \ 196 goto fault; \ 197 } while (0) 198 199 #define get32_unaligned_check(val,addr) \ 200 __get32_unaligned_check("ldrb",val,addr) 201 202 #define get32t_unaligned_check(val,addr) \ 203 __get32_unaligned_check("ldrbt",val,addr) 204 205 #define __put16_unaligned_check(ins,val,addr) \ 206 do { \ 207 unsigned int err = 0, v = val, a = addr; \ 208 __asm__( FIRST_BYTE_16 \ 209 "1: "ins" %1, [%2], #1\n" \ 210 " mov %1, %1, "NEXT_BYTE"\n" \ 211 "2: "ins" %1, [%2]\n" \ 212 "3:\n" \ 213 " .section .fixup,\"ax\"\n" \ 214 " .align 2\n" \ 215 "4: mov %0, #1\n" \ 216 " b 3b\n" \ 217 " .previous\n" \ 218 " .section __ex_table,\"a\"\n" \ 219 " .align 3\n" \ 220 " .long 1b, 4b\n" \ 221 " .long 2b, 4b\n" \ 222 " .previous\n" \ 223 : "=r" (err), "=&r" (v), "=&r" (a) \ 224 : "0" (err), "1" (v), "2" (a)); \ 225 if (err) \ 226 goto fault; \ 227 } while (0) 228 229 #define put16_unaligned_check(val,addr) \ 230 __put16_unaligned_check("strb",val,addr) 231 232 #define put16t_unaligned_check(val,addr) \ 233 __put16_unaligned_check("strbt",val,addr) 234 235 #define __put32_unaligned_check(ins,val,addr) \ 236 do { \ 237 unsigned int err = 0, v = val, a = addr; \ 238 __asm__( FIRST_BYTE_32 \ 239 "1: "ins" %1, [%2], #1\n" \ 240 " mov %1, %1, "NEXT_BYTE"\n" \ 241 "2: "ins" %1, [%2], #1\n" \ 242 " mov %1, %1, "NEXT_BYTE"\n" \ 243 "3: "ins" %1, [%2], #1\n" \ 244 " mov %1, %1, "NEXT_BYTE"\n" \ 245 "4: "ins" %1, [%2]\n" \ 246 "5:\n" \ 247 " .section .fixup,\"ax\"\n" \ 248 " .align 2\n" \ 249 "6: mov %0, #1\n" \ 250 " b 5b\n" \ 251 " .previous\n" \ 252 " .section __ex_table,\"a\"\n" \ 253 " .align 3\n" \ 254 " .long 1b, 6b\n" \ 255 " .long 2b, 6b\n" \ 256 " .long 3b, 6b\n" \ 257 " .long 4b, 6b\n" \ 258 " .previous\n" \ 259 : "=r" (err), "=&r" (v), "=&r" (a) \ 260 : "0" (err), "1" (v), "2" (a)); \ 261 if (err) \ 262 goto fault; \ 263 } while (0) 264 265 #define put32_unaligned_check(val,addr) \ 266 __put32_unaligned_check("strb", val, addr) 267 268 #define put32t_unaligned_check(val,addr) \ 269 __put32_unaligned_check("strbt", val, addr) 270 271 static void 272 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset) 273 { 274 if (!LDST_U_BIT(instr)) 275 offset.un = -offset.un; 276 277 if (!LDST_P_BIT(instr)) 278 addr += offset.un; 279 280 if (!LDST_P_BIT(instr) || LDST_W_BIT(instr)) 281 regs->uregs[RN_BITS(instr)] = addr; 282 } 283 284 static int 285 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs) 286 { 287 unsigned int rd = RD_BITS(instr); 288 289 ai_half += 1; 290 291 if (user_mode(regs)) 292 goto user; 293 294 if (LDST_L_BIT(instr)) { 295 unsigned long val; 296 get16_unaligned_check(val, addr); 297 298 /* signed half-word? */ 299 if (instr & 0x40) 300 val = (signed long)((signed short) val); 301 302 regs->uregs[rd] = val; 303 } else 304 put16_unaligned_check(regs->uregs[rd], addr); 305 306 return TYPE_LDST; 307 308 user: 309 if (LDST_L_BIT(instr)) { 310 unsigned long val; 311 get16t_unaligned_check(val, addr); 312 313 /* signed half-word? */ 314 if (instr & 0x40) 315 val = (signed long)((signed short) val); 316 317 regs->uregs[rd] = val; 318 } else 319 put16t_unaligned_check(regs->uregs[rd], addr); 320 321 return TYPE_LDST; 322 323 fault: 324 return TYPE_FAULT; 325 } 326 327 static int 328 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr, 329 struct pt_regs *regs) 330 { 331 unsigned int rd = RD_BITS(instr); 332 333 ai_dword += 1; 334 335 if (user_mode(regs)) 336 goto user; 337 338 if ((instr & 0xf0) == 0xd0) { 339 unsigned long val; 340 get32_unaligned_check(val, addr); 341 regs->uregs[rd] = val; 342 get32_unaligned_check(val, addr+4); 343 regs->uregs[rd+1] = val; 344 } else { 345 put32_unaligned_check(regs->uregs[rd], addr); 346 put32_unaligned_check(regs->uregs[rd+1], addr+4); 347 } 348 349 return TYPE_LDST; 350 351 user: 352 if ((instr & 0xf0) == 0xd0) { 353 unsigned long val; 354 get32t_unaligned_check(val, addr); 355 regs->uregs[rd] = val; 356 get32t_unaligned_check(val, addr+4); 357 regs->uregs[rd+1] = val; 358 } else { 359 put32t_unaligned_check(regs->uregs[rd], addr); 360 put32t_unaligned_check(regs->uregs[rd+1], addr+4); 361 } 362 363 return TYPE_LDST; 364 365 fault: 366 return TYPE_FAULT; 367 } 368 369 static int 370 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs) 371 { 372 unsigned int rd = RD_BITS(instr); 373 374 ai_word += 1; 375 376 if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs)) 377 goto trans; 378 379 if (LDST_L_BIT(instr)) { 380 unsigned int val; 381 get32_unaligned_check(val, addr); 382 regs->uregs[rd] = val; 383 } else 384 put32_unaligned_check(regs->uregs[rd], addr); 385 return TYPE_LDST; 386 387 trans: 388 if (LDST_L_BIT(instr)) { 389 unsigned int val; 390 get32t_unaligned_check(val, addr); 391 regs->uregs[rd] = val; 392 } else 393 put32t_unaligned_check(regs->uregs[rd], addr); 394 return TYPE_LDST; 395 396 fault: 397 return TYPE_FAULT; 398 } 399 400 /* 401 * LDM/STM alignment handler. 402 * 403 * There are 4 variants of this instruction: 404 * 405 * B = rn pointer before instruction, A = rn pointer after instruction 406 * ------ increasing address -----> 407 * | | r0 | r1 | ... | rx | | 408 * PU = 01 B A 409 * PU = 11 B A 410 * PU = 00 A B 411 * PU = 10 A B 412 */ 413 static int 414 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs) 415 { 416 unsigned int rd, rn, correction, nr_regs, regbits; 417 unsigned long eaddr, newaddr; 418 419 if (LDM_S_BIT(instr)) 420 goto bad; 421 422 correction = 4; /* processor implementation defined */ 423 regs->ARM_pc += correction; 424 425 ai_multi += 1; 426 427 /* count the number of registers in the mask to be transferred */ 428 nr_regs = hweight16(REGMASK_BITS(instr)) * 4; 429 430 rn = RN_BITS(instr); 431 newaddr = eaddr = regs->uregs[rn]; 432 433 if (!LDST_U_BIT(instr)) 434 nr_regs = -nr_regs; 435 newaddr += nr_regs; 436 if (!LDST_U_BIT(instr)) 437 eaddr = newaddr; 438 439 if (LDST_P_EQ_U(instr)) /* U = P */ 440 eaddr += 4; 441 442 /* 443 * For alignment faults on the ARM922T/ARM920T the MMU makes 444 * the FSR (and hence addr) equal to the updated base address 445 * of the multiple access rather than the restored value. 446 * Switch this message off if we've got a ARM92[02], otherwise 447 * [ls]dm alignment faults are noisy! 448 */ 449 #if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T) 450 /* 451 * This is a "hint" - we already have eaddr worked out by the 452 * processor for us. 453 */ 454 if (addr != eaddr) { 455 printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, " 456 "addr = %08lx, eaddr = %08lx\n", 457 instruction_pointer(regs), instr, addr, eaddr); 458 show_regs(regs); 459 } 460 #endif 461 462 if (user_mode(regs)) { 463 for (regbits = REGMASK_BITS(instr), rd = 0; regbits; 464 regbits >>= 1, rd += 1) 465 if (regbits & 1) { 466 if (LDST_L_BIT(instr)) { 467 unsigned int val; 468 get32t_unaligned_check(val, eaddr); 469 regs->uregs[rd] = val; 470 } else 471 put32t_unaligned_check(regs->uregs[rd], eaddr); 472 eaddr += 4; 473 } 474 } else { 475 for (regbits = REGMASK_BITS(instr), rd = 0; regbits; 476 regbits >>= 1, rd += 1) 477 if (regbits & 1) { 478 if (LDST_L_BIT(instr)) { 479 unsigned int val; 480 get32_unaligned_check(val, eaddr); 481 regs->uregs[rd] = val; 482 } else 483 put32_unaligned_check(regs->uregs[rd], eaddr); 484 eaddr += 4; 485 } 486 } 487 488 if (LDST_W_BIT(instr)) 489 regs->uregs[rn] = newaddr; 490 if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15))) 491 regs->ARM_pc -= correction; 492 return TYPE_DONE; 493 494 fault: 495 regs->ARM_pc -= correction; 496 return TYPE_FAULT; 497 498 bad: 499 printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n"); 500 return TYPE_ERROR; 501 } 502 503 /* 504 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so 505 * we can reuse ARM userland alignment fault fixups for Thumb. 506 * 507 * This implementation was initially based on the algorithm found in 508 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same 509 * to convert only Thumb ld/st instruction forms to equivalent ARM forms. 510 * 511 * NOTES: 512 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections. 513 * 2. If for some reason we're passed an non-ld/st Thumb instruction to 514 * decode, we return 0xdeadc0de. This should never happen under normal 515 * circumstances but if it does, we've got other problems to deal with 516 * elsewhere and we obviously can't fix those problems here. 517 */ 518 519 static unsigned long 520 thumb2arm(u16 tinstr) 521 { 522 u32 L = (tinstr & (1<<11)) >> 11; 523 524 switch ((tinstr & 0xf800) >> 11) { 525 /* 6.5.1 Format 1: */ 526 case 0x6000 >> 11: /* 7.1.52 STR(1) */ 527 case 0x6800 >> 11: /* 7.1.26 LDR(1) */ 528 case 0x7000 >> 11: /* 7.1.55 STRB(1) */ 529 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */ 530 return 0xe5800000 | 531 ((tinstr & (1<<12)) << (22-12)) | /* fixup */ 532 (L<<20) | /* L==1? */ 533 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 534 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 535 ((tinstr & (31<<6)) >> /* immed_5 */ 536 (6 - ((tinstr & (1<<12)) ? 0 : 2))); 537 case 0x8000 >> 11: /* 7.1.57 STRH(1) */ 538 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */ 539 return 0xe1c000b0 | 540 (L<<20) | /* L==1? */ 541 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 542 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 543 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */ 544 ((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */ 545 546 /* 6.5.1 Format 2: */ 547 case 0x5000 >> 11: 548 case 0x5800 >> 11: 549 { 550 static const u32 subset[8] = { 551 0xe7800000, /* 7.1.53 STR(2) */ 552 0xe18000b0, /* 7.1.58 STRH(2) */ 553 0xe7c00000, /* 7.1.56 STRB(2) */ 554 0xe19000d0, /* 7.1.34 LDRSB */ 555 0xe7900000, /* 7.1.27 LDR(2) */ 556 0xe19000b0, /* 7.1.33 LDRH(2) */ 557 0xe7d00000, /* 7.1.31 LDRB(2) */ 558 0xe19000f0 /* 7.1.35 LDRSH */ 559 }; 560 return subset[(tinstr & (7<<9)) >> 9] | 561 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 562 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 563 ((tinstr & (7<<6)) >> (6-0)); /* Rm */ 564 } 565 566 /* 6.5.1 Format 3: */ 567 case 0x4800 >> 11: /* 7.1.28 LDR(3) */ 568 /* NOTE: This case is not technically possible. We're 569 * loading 32-bit memory data via PC relative 570 * addressing mode. So we can and should eliminate 571 * this case. But I'll leave it here for now. 572 */ 573 return 0xe59f0000 | 574 ((tinstr & (7<<8)) << (12-8)) | /* Rd */ 575 ((tinstr & 255) << (2-0)); /* immed_8 */ 576 577 /* 6.5.1 Format 4: */ 578 case 0x9000 >> 11: /* 7.1.54 STR(3) */ 579 case 0x9800 >> 11: /* 7.1.29 LDR(4) */ 580 return 0xe58d0000 | 581 (L<<20) | /* L==1? */ 582 ((tinstr & (7<<8)) << (12-8)) | /* Rd */ 583 ((tinstr & 255) << 2); /* immed_8 */ 584 585 /* 6.6.1 Format 1: */ 586 case 0xc000 >> 11: /* 7.1.51 STMIA */ 587 case 0xc800 >> 11: /* 7.1.25 LDMIA */ 588 { 589 u32 Rn = (tinstr & (7<<8)) >> 8; 590 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21; 591 592 return 0xe8800000 | W | (L<<20) | (Rn<<16) | 593 (tinstr&255); 594 } 595 596 /* 6.6.1 Format 2: */ 597 case 0xb000 >> 11: /* 7.1.48 PUSH */ 598 case 0xb800 >> 11: /* 7.1.47 POP */ 599 if ((tinstr & (3 << 9)) == 0x0400) { 600 static const u32 subset[4] = { 601 0xe92d0000, /* STMDB sp!,{registers} */ 602 0xe92d4000, /* STMDB sp!,{registers,lr} */ 603 0xe8bd0000, /* LDMIA sp!,{registers} */ 604 0xe8bd8000 /* LDMIA sp!,{registers,pc} */ 605 }; 606 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] | 607 (tinstr & 255); /* register_list */ 608 } 609 /* Else fall through for illegal instruction case */ 610 611 default: 612 return 0xdeadc0de; 613 } 614 } 615 616 static int 617 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 618 { 619 union offset_union offset; 620 unsigned long instr = 0, instrptr; 621 int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs); 622 unsigned int type; 623 mm_segment_t fs; 624 unsigned int fault; 625 u16 tinstr = 0; 626 627 instrptr = instruction_pointer(regs); 628 629 fs = get_fs(); 630 set_fs(KERNEL_DS); 631 if thumb_mode(regs) { 632 fault = __get_user(tinstr, (u16 *)(instrptr & ~1)); 633 if (!(fault)) 634 instr = thumb2arm(tinstr); 635 } else 636 fault = __get_user(instr, (u32 *)instrptr); 637 set_fs(fs); 638 639 if (fault) { 640 type = TYPE_FAULT; 641 goto bad_or_fault; 642 } 643 644 if (user_mode(regs)) 645 goto user; 646 647 ai_sys += 1; 648 649 fixup: 650 651 regs->ARM_pc += thumb_mode(regs) ? 2 : 4; 652 653 switch (CODING_BITS(instr)) { 654 case 0x00000000: /* 3.13.4 load/store instruction extensions */ 655 if (LDSTHD_I_BIT(instr)) 656 offset.un = (instr & 0xf00) >> 4 | (instr & 15); 657 else 658 offset.un = regs->uregs[RM_BITS(instr)]; 659 660 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */ 661 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */ 662 handler = do_alignment_ldrhstrh; 663 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */ 664 (instr & 0x001000f0) == 0x000000f0) /* STRD */ 665 handler = do_alignment_ldrdstrd; 666 else 667 goto bad; 668 break; 669 670 case 0x04000000: /* ldr or str immediate */ 671 offset.un = OFFSET_BITS(instr); 672 handler = do_alignment_ldrstr; 673 break; 674 675 case 0x06000000: /* ldr or str register */ 676 offset.un = regs->uregs[RM_BITS(instr)]; 677 678 if (IS_SHIFT(instr)) { 679 unsigned int shiftval = SHIFT_BITS(instr); 680 681 switch(SHIFT_TYPE(instr)) { 682 case SHIFT_LSL: 683 offset.un <<= shiftval; 684 break; 685 686 case SHIFT_LSR: 687 offset.un >>= shiftval; 688 break; 689 690 case SHIFT_ASR: 691 offset.sn >>= shiftval; 692 break; 693 694 case SHIFT_RORRRX: 695 if (shiftval == 0) { 696 offset.un >>= 1; 697 if (regs->ARM_cpsr & PSR_C_BIT) 698 offset.un |= 1 << 31; 699 } else 700 offset.un = offset.un >> shiftval | 701 offset.un << (32 - shiftval); 702 break; 703 } 704 } 705 handler = do_alignment_ldrstr; 706 break; 707 708 case 0x08000000: /* ldm or stm */ 709 handler = do_alignment_ldmstm; 710 break; 711 712 default: 713 goto bad; 714 } 715 716 type = handler(addr, instr, regs); 717 718 if (type == TYPE_ERROR || type == TYPE_FAULT) 719 goto bad_or_fault; 720 721 if (type == TYPE_LDST) 722 do_alignment_finish_ldst(addr, instr, regs, offset); 723 724 return 0; 725 726 bad_or_fault: 727 if (type == TYPE_ERROR) 728 goto bad; 729 regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; 730 /* 731 * We got a fault - fix it up, or die. 732 */ 733 do_bad_area(current, current->mm, addr, fsr, regs); 734 return 0; 735 736 bad: 737 /* 738 * Oops, we didn't handle the instruction. 739 */ 740 printk(KERN_ERR "Alignment trap: not handling instruction " 741 "%0*lx at [<%08lx>]\n", 742 thumb_mode(regs) ? 4 : 8, 743 thumb_mode(regs) ? tinstr : instr, instrptr); 744 ai_skipped += 1; 745 return 1; 746 747 user: 748 ai_user += 1; 749 750 if (ai_usermode & 1) 751 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx " 752 "Address=0x%08lx FSR 0x%03x\n", current->comm, 753 current->pid, instrptr, 754 thumb_mode(regs) ? 4 : 8, 755 thumb_mode(regs) ? tinstr : instr, 756 addr, fsr); 757 758 if (ai_usermode & 2) 759 goto fixup; 760 761 if (ai_usermode & 4) 762 force_sig(SIGBUS, current); 763 else 764 set_cr(cr_no_alignment); 765 766 return 0; 767 } 768 769 /* 770 * This needs to be done after sysctl_init, otherwise sys/ will be 771 * overwritten. Actually, this shouldn't be in sys/ at all since 772 * it isn't a sysctl, and it doesn't contain sysctl information. 773 * We now locate it in /proc/cpu/alignment instead. 774 */ 775 static int __init alignment_init(void) 776 { 777 #ifdef CONFIG_PROC_FS 778 struct proc_dir_entry *res; 779 780 res = proc_mkdir("cpu", NULL); 781 if (!res) 782 return -ENOMEM; 783 784 res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res); 785 if (!res) 786 return -ENOMEM; 787 788 res->read_proc = proc_alignment_read; 789 res->write_proc = proc_alignment_write; 790 #endif 791 792 hook_fault_code(1, do_alignment, SIGILL, "alignment exception"); 793 hook_fault_code(3, do_alignment, SIGILL, "alignment exception"); 794 795 return 0; 796 } 797 798 fs_initcall(alignment_init); 799