1comment "Processor Type" 2 3config CPU_32 4 bool 5 default y 6 7# Select CPU types depending on the architecture selected. This selects 8# which CPUs we support in the kernel image, and the compiler instruction 9# optimiser behaviour. 10 11# ARM610 12config CPU_ARM610 13 bool "Support ARM610 processor" 14 depends on ARCH_RPC 15 select CPU_32v3 16 select CPU_CACHE_V3 17 select CPU_CACHE_VIVT 18 select CPU_CP15_MMU 19 select CPU_COPY_V3 if MMU 20 select CPU_TLB_V3 if MMU 21 help 22 The ARM610 is the successor to the ARM3 processor 23 and was produced by VLSI Technology Inc. 24 25 Say Y if you want support for the ARM610 processor. 26 Otherwise, say N. 27 28# ARM710 29config CPU_ARM710 30 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC 31 default y if ARCH_CLPS7500 32 select CPU_32v3 33 select CPU_CACHE_V3 34 select CPU_CACHE_VIVT 35 select CPU_CP15_MMU 36 select CPU_COPY_V3 if MMU 37 select CPU_TLB_V3 if MMU 38 help 39 A 32-bit RISC microprocessor based on the ARM7 processor core 40 designed by Advanced RISC Machines Ltd. The ARM710 is the 41 successor to the ARM610 processor. It was released in 42 July 1994 by VLSI Technology Inc. 43 44 Say Y if you want support for the ARM710 processor. 45 Otherwise, say N. 46 47# ARM720T 48config CPU_ARM720T 49 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR 50 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X 51 select CPU_32v4T 52 select CPU_ABRT_LV4T 53 select CPU_CACHE_V4 54 select CPU_CACHE_VIVT 55 select CPU_CP15_MMU 56 select CPU_COPY_V4WT if MMU 57 select CPU_TLB_V4WT if MMU 58 help 59 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 60 MMU built around an ARM7TDMI core. 61 62 Say Y if you want support for the ARM720T processor. 63 Otherwise, say N. 64 65# ARM920T 66config CPU_ARM920T 67 bool "Support ARM920T processor" 68 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 69 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 70 select CPU_32v4T 71 select CPU_ABRT_EV4T 72 select CPU_CACHE_V4WT 73 select CPU_CACHE_VIVT 74 select CPU_CP15_MMU 75 select CPU_COPY_V4WB if MMU 76 select CPU_TLB_V4WBI if MMU 77 help 78 The ARM920T is licensed to be produced by numerous vendors, 79 and is used in the Maverick EP9312 and the Samsung S3C2410. 80 81 More information on the Maverick EP9312 at 82 <http://linuxdevices.com/products/PD2382866068.html>. 83 84 Say Y if you want support for the ARM920T processor. 85 Otherwise, say N. 86 87# ARM922T 88config CPU_ARM922T 89 bool "Support ARM922T processor" if ARCH_INTEGRATOR 90 depends on ARCH_LH7A40X || ARCH_INTEGRATOR 91 default y if ARCH_LH7A40X 92 select CPU_32v4T 93 select CPU_ABRT_EV4T 94 select CPU_CACHE_V4WT 95 select CPU_CACHE_VIVT 96 select CPU_CP15_MMU 97 select CPU_COPY_V4WB if MMU 98 select CPU_TLB_V4WBI if MMU 99 help 100 The ARM922T is a version of the ARM920T, but with smaller 101 instruction and data caches. It is used in Altera's 102 Excalibur XA device family. 103 104 Say Y if you want support for the ARM922T processor. 105 Otherwise, say N. 106 107# ARM925T 108config CPU_ARM925T 109 bool "Support ARM925T processor" if ARCH_OMAP1 110 depends on ARCH_OMAP15XX 111 default y if ARCH_OMAP15XX 112 select CPU_32v4T 113 select CPU_ABRT_EV4T 114 select CPU_CACHE_V4WT 115 select CPU_CACHE_VIVT 116 select CPU_CP15_MMU 117 select CPU_COPY_V4WB if MMU 118 select CPU_TLB_V4WBI if MMU 119 help 120 The ARM925T is a mix between the ARM920T and ARM926T, but with 121 different instruction and data caches. It is used in TI's OMAP 122 device family. 123 124 Say Y if you want support for the ARM925T processor. 125 Otherwise, say N. 126 127# ARM926T 128config CPU_ARM926T 129 bool "Support ARM926T processor" 130 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 131 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 132 select CPU_32v5 133 select CPU_ABRT_EV5TJ 134 select CPU_CACHE_VIVT 135 select CPU_CP15_MMU 136 select CPU_COPY_V4WB if MMU 137 select CPU_TLB_V4WBI if MMU 138 help 139 This is a variant of the ARM920. It has slightly different 140 instruction sequences for cache and TLB operations. Curiously, 141 there is no documentation on it at the ARM corporate website. 142 143 Say Y if you want support for the ARM926T processor. 144 Otherwise, say N. 145 146# ARM1020 - needs validating 147config CPU_ARM1020 148 bool "Support ARM1020T (rev 0) processor" 149 depends on ARCH_INTEGRATOR 150 select CPU_32v5 151 select CPU_ABRT_EV4T 152 select CPU_CACHE_V4WT 153 select CPU_CACHE_VIVT 154 select CPU_CP15_MMU 155 select CPU_COPY_V4WB if MMU 156 select CPU_TLB_V4WBI if MMU 157 help 158 The ARM1020 is the 32K cached version of the ARM10 processor, 159 with an addition of a floating-point unit. 160 161 Say Y if you want support for the ARM1020 processor. 162 Otherwise, say N. 163 164# ARM1020E - needs validating 165config CPU_ARM1020E 166 bool "Support ARM1020E processor" 167 depends on ARCH_INTEGRATOR 168 select CPU_32v5 169 select CPU_ABRT_EV4T 170 select CPU_CACHE_V4WT 171 select CPU_CACHE_VIVT 172 select CPU_CP15_MMU 173 select CPU_COPY_V4WB if MMU 174 select CPU_TLB_V4WBI if MMU 175 depends on n 176 177# ARM1022E 178config CPU_ARM1022 179 bool "Support ARM1022E processor" 180 depends on ARCH_INTEGRATOR 181 select CPU_32v5 182 select CPU_ABRT_EV4T 183 select CPU_CACHE_VIVT 184 select CPU_CP15_MMU 185 select CPU_COPY_V4WB if MMU # can probably do better 186 select CPU_TLB_V4WBI if MMU 187 help 188 The ARM1022E is an implementation of the ARMv5TE architecture 189 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 190 embedded trace macrocell, and a floating-point unit. 191 192 Say Y if you want support for the ARM1022E processor. 193 Otherwise, say N. 194 195# ARM1026EJ-S 196config CPU_ARM1026 197 bool "Support ARM1026EJ-S processor" 198 depends on ARCH_INTEGRATOR 199 select CPU_32v5 200 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 201 select CPU_CACHE_VIVT 202 select CPU_CP15_MMU 203 select CPU_COPY_V4WB if MMU # can probably do better 204 select CPU_TLB_V4WBI if MMU 205 help 206 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 207 based upon the ARM10 integer core. 208 209 Say Y if you want support for the ARM1026EJ-S processor. 210 Otherwise, say N. 211 212# SA110 213config CPU_SA110 214 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC 215 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI 216 select CPU_32v3 if ARCH_RPC 217 select CPU_32v4 if !ARCH_RPC 218 select CPU_ABRT_EV4 219 select CPU_CACHE_V4WB 220 select CPU_CACHE_VIVT 221 select CPU_CP15_MMU 222 select CPU_COPY_V4WB if MMU 223 select CPU_TLB_V4WB if MMU 224 help 225 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 226 is available at five speeds ranging from 100 MHz to 233 MHz. 227 More information is available at 228 <http://developer.intel.com/design/strong/sa110.htm>. 229 230 Say Y if you want support for the SA-110 processor. 231 Otherwise, say N. 232 233# SA1100 234config CPU_SA1100 235 bool 236 depends on ARCH_SA1100 237 default y 238 select CPU_32v4 239 select CPU_ABRT_EV4 240 select CPU_CACHE_V4WB 241 select CPU_CACHE_VIVT 242 select CPU_CP15_MMU 243 select CPU_TLB_V4WB if MMU 244 245# XScale 246config CPU_XSCALE 247 bool 248 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 249 default y 250 select CPU_32v5 251 select CPU_ABRT_EV5T 252 select CPU_CACHE_VIVT 253 select CPU_CP15_MMU 254 select CPU_TLB_V4WBI if MMU 255 256# XScale Core Version 3 257config CPU_XSC3 258 bool 259 depends on ARCH_IXP23XX 260 default y 261 select CPU_32v5 262 select CPU_ABRT_EV5T 263 select CPU_CACHE_VIVT 264 select CPU_CP15_MMU 265 select CPU_TLB_V4WBI if MMU 266 select IO_36 267 268# ARMv6 269config CPU_V6 270 bool "Support ARM V6 processor" 271 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 272 select CPU_32v6 273 select CPU_ABRT_EV6 274 select CPU_CACHE_V6 275 select CPU_CACHE_VIPT 276 select CPU_CP15_MMU 277 select CPU_COPY_V6 if MMU 278 select CPU_TLB_V6 if MMU 279 280# ARMv6k 281config CPU_32v6K 282 bool "Support ARM V6K processor extensions" if !SMP 283 depends on CPU_V6 284 default y if SMP 285 help 286 Say Y here if your ARMv6 processor supports the 'K' extension. 287 This enables the kernel to use some instructions not present 288 on previous processors, and as such a kernel build with this 289 enabled will not boot on processors with do not support these 290 instructions. 291 292# Figure out what processor architecture version we should be using. 293# This defines the compiler instruction set which depends on the machine type. 294config CPU_32v3 295 bool 296 select TLS_REG_EMUL if SMP || !MMU 297 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 298 299config CPU_32v4 300 bool 301 select TLS_REG_EMUL if SMP || !MMU 302 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 303 304config CPU_32v4T 305 bool 306 select TLS_REG_EMUL if SMP || !MMU 307 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 308 309config CPU_32v5 310 bool 311 select TLS_REG_EMUL if SMP || !MMU 312 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 313 314config CPU_32v6 315 bool 316 317# The abort model 318config CPU_ABRT_EV4 319 bool 320 321config CPU_ABRT_EV4T 322 bool 323 324config CPU_ABRT_LV4T 325 bool 326 327config CPU_ABRT_EV5T 328 bool 329 330config CPU_ABRT_EV5TJ 331 bool 332 333config CPU_ABRT_EV6 334 bool 335 336# The cache model 337config CPU_CACHE_V3 338 bool 339 340config CPU_CACHE_V4 341 bool 342 343config CPU_CACHE_V4WT 344 bool 345 346config CPU_CACHE_V4WB 347 bool 348 349config CPU_CACHE_V6 350 bool 351 352config CPU_CACHE_VIVT 353 bool 354 355config CPU_CACHE_VIPT 356 bool 357 358if MMU 359# The copy-page model 360config CPU_COPY_V3 361 bool 362 363config CPU_COPY_V4WT 364 bool 365 366config CPU_COPY_V4WB 367 bool 368 369config CPU_COPY_V6 370 bool 371 372# This selects the TLB model 373config CPU_TLB_V3 374 bool 375 help 376 ARM Architecture Version 3 TLB. 377 378config CPU_TLB_V4WT 379 bool 380 help 381 ARM Architecture Version 4 TLB with writethrough cache. 382 383config CPU_TLB_V4WB 384 bool 385 help 386 ARM Architecture Version 4 TLB with writeback cache. 387 388config CPU_TLB_V4WBI 389 bool 390 help 391 ARM Architecture Version 4 TLB with writeback cache and invalidate 392 instruction cache entry. 393 394config CPU_TLB_V6 395 bool 396 397endif 398 399config CPU_CP15 400 bool 401 help 402 Processor has the CP15 register. 403 404config CPU_CP15_MMU 405 bool 406 select CPU_CP15 407 help 408 Processor has the CP15 register, which has MMU related registers. 409 410config CPU_CP15_MPU 411 bool 412 select CPU_CP15 413 help 414 Processor has the CP15 register, which has MPU related registers. 415 416# 417# CPU supports 36-bit I/O 418# 419config IO_36 420 bool 421 422comment "Processor Features" 423 424config ARM_THUMB 425 bool "Support Thumb user binaries" 426 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 427 default y 428 help 429 Say Y if you want to include kernel support for running user space 430 Thumb binaries. 431 432 The Thumb instruction set is a compressed form of the standard ARM 433 instruction set resulting in smaller binaries at the expense of 434 slightly less efficient code. 435 436 If you don't know what this all is, saying Y is a safe choice. 437 438config CPU_BIG_ENDIAN 439 bool "Build big-endian kernel" 440 depends on ARCH_SUPPORTS_BIG_ENDIAN 441 help 442 Say Y if you plan on running a kernel in big-endian mode. 443 Note that your board must be properly built and your board 444 port must properly enable any big-endian related features 445 of your chipset/board/processor. 446 447config CPU_ICACHE_DISABLE 448 bool "Disable I-Cache" 449 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 450 help 451 Say Y here to disable the processor instruction cache. Unless 452 you have a reason not to or are unsure, say N. 453 454config CPU_DCACHE_DISABLE 455 bool "Disable D-Cache" 456 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 457 help 458 Say Y here to disable the processor data cache. Unless 459 you have a reason not to or are unsure, say N. 460 461config CPU_DCACHE_WRITETHROUGH 462 bool "Force write through D-cache" 463 depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE 464 default y if CPU_ARM925T 465 help 466 Say Y here to use the data cache in writethrough mode. Unless you 467 specifically require this or are unsure, say N. 468 469config CPU_CACHE_ROUND_ROBIN 470 bool "Round robin I and D cache replacement algorithm" 471 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 472 help 473 Say Y here to use the predictable round-robin cache replacement 474 policy. Unless you specifically require this or are unsure, say N. 475 476config CPU_BPREDICT_DISABLE 477 bool "Disable branch prediction" 478 depends on CPU_ARM1020 || CPU_V6 479 help 480 Say Y here to disable branch prediction. If unsure, say N. 481 482config TLS_REG_EMUL 483 bool 484 help 485 An SMP system using a pre-ARMv6 processor (there are apparently 486 a few prototypes like that in existence) and therefore access to 487 that required register must be emulated. 488 489config HAS_TLS_REG 490 bool 491 depends on !TLS_REG_EMUL 492 default y if SMP || CPU_32v7 493 help 494 This selects support for the CP15 thread register. 495 It is defined to be available on some ARMv6 processors (including 496 all SMP capable ARMv6's) or later processors. User space may 497 assume directly accessing that register and always obtain the 498 expected value only on ARMv7 and above. 499 500config NEEDS_SYSCALL_FOR_CMPXCHG 501 bool 502 help 503 SMP on a pre-ARMv6 processor? Well OK then. 504 Forget about fast user space cmpxchg support. 505 It is just not possible. 506 507