1comment "Processor Type" 2 3config CPU_32 4 bool 5 default y 6 7# Select CPU types depending on the architecture selected. This selects 8# which CPUs we support in the kernel image, and the compiler instruction 9# optimiser behaviour. 10 11# ARM610 12config CPU_ARM610 13 bool "Support ARM610 processor" 14 depends on ARCH_RPC 15 select CPU_32v3 16 select CPU_CACHE_V3 17 select CPU_CACHE_VIVT 18 select CPU_CP15_MMU 19 select CPU_COPY_V3 if MMU 20 select CPU_TLB_V3 if MMU 21 select CPU_PABRT_NOIFAR 22 help 23 The ARM610 is the successor to the ARM3 processor 24 and was produced by VLSI Technology Inc. 25 26 Say Y if you want support for the ARM610 processor. 27 Otherwise, say N. 28 29# ARM7TDMI 30config CPU_ARM7TDMI 31 bool "Support ARM7TDMI processor" 32 depends on !MMU 33 select CPU_32v4T 34 select CPU_ABRT_LV4T 35 select CPU_PABRT_NOIFAR 36 select CPU_CACHE_V4 37 help 38 A 32-bit RISC microprocessor based on the ARM7 processor core 39 which has no memory control unit and cache. 40 41 Say Y if you want support for the ARM7TDMI processor. 42 Otherwise, say N. 43 44# ARM710 45config CPU_ARM710 46 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC 47 default y if ARCH_CLPS7500 48 select CPU_32v3 49 select CPU_CACHE_V3 50 select CPU_CACHE_VIVT 51 select CPU_CP15_MMU 52 select CPU_COPY_V3 if MMU 53 select CPU_TLB_V3 if MMU 54 select CPU_PABRT_NOIFAR 55 help 56 A 32-bit RISC microprocessor based on the ARM7 processor core 57 designed by Advanced RISC Machines Ltd. The ARM710 is the 58 successor to the ARM610 processor. It was released in 59 July 1994 by VLSI Technology Inc. 60 61 Say Y if you want support for the ARM710 processor. 62 Otherwise, say N. 63 64# ARM720T 65config CPU_ARM720T 66 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR 67 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X 68 select CPU_32v4T 69 select CPU_ABRT_LV4T 70 select CPU_PABRT_NOIFAR 71 select CPU_CACHE_V4 72 select CPU_CACHE_VIVT 73 select CPU_CP15_MMU 74 select CPU_COPY_V4WT if MMU 75 select CPU_TLB_V4WT if MMU 76 help 77 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 78 MMU built around an ARM7TDMI core. 79 80 Say Y if you want support for the ARM720T processor. 81 Otherwise, say N. 82 83# ARM740T 84config CPU_ARM740T 85 bool "Support ARM740T processor" if ARCH_INTEGRATOR 86 depends on !MMU 87 select CPU_32v4T 88 select CPU_ABRT_LV4T 89 select CPU_PABRT_NOIFAR 90 select CPU_CACHE_V3 # although the core is v4t 91 select CPU_CP15_MPU 92 help 93 A 32-bit RISC processor with 8KB cache or 4KB variants, 94 write buffer and MPU(Protection Unit) built around 95 an ARM7TDMI core. 96 97 Say Y if you want support for the ARM740T processor. 98 Otherwise, say N. 99 100# ARM9TDMI 101config CPU_ARM9TDMI 102 bool "Support ARM9TDMI processor" 103 depends on !MMU 104 select CPU_32v4T 105 select CPU_ABRT_NOMMU 106 select CPU_PABRT_NOIFAR 107 select CPU_CACHE_V4 108 help 109 A 32-bit RISC microprocessor based on the ARM9 processor core 110 which has no memory control unit and cache. 111 112 Say Y if you want support for the ARM9TDMI processor. 113 Otherwise, say N. 114 115# ARM920T 116config CPU_ARM920T 117 bool "Support ARM920T processor" 118 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 119 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 120 select CPU_32v4T 121 select CPU_ABRT_EV4T 122 select CPU_PABRT_NOIFAR 123 select CPU_CACHE_V4WT 124 select CPU_CACHE_VIVT 125 select CPU_CP15_MMU 126 select CPU_COPY_V4WB if MMU 127 select CPU_TLB_V4WBI if MMU 128 help 129 The ARM920T is licensed to be produced by numerous vendors, 130 and is used in the Maverick EP9312 and the Samsung S3C2410. 131 132 More information on the Maverick EP9312 at 133 <http://linuxdevices.com/products/PD2382866068.html>. 134 135 Say Y if you want support for the ARM920T processor. 136 Otherwise, say N. 137 138# ARM922T 139config CPU_ARM922T 140 bool "Support ARM922T processor" if ARCH_INTEGRATOR 141 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695 142 default y if ARCH_LH7A40X || ARCH_KS8695 143 select CPU_32v4T 144 select CPU_ABRT_EV4T 145 select CPU_PABRT_NOIFAR 146 select CPU_CACHE_V4WT 147 select CPU_CACHE_VIVT 148 select CPU_CP15_MMU 149 select CPU_COPY_V4WB if MMU 150 select CPU_TLB_V4WBI if MMU 151 help 152 The ARM922T is a version of the ARM920T, but with smaller 153 instruction and data caches. It is used in Altera's 154 Excalibur XA device family and Micrel's KS8695 Centaur. 155 156 Say Y if you want support for the ARM922T processor. 157 Otherwise, say N. 158 159# ARM925T 160config CPU_ARM925T 161 bool "Support ARM925T processor" if ARCH_OMAP1 162 depends on ARCH_OMAP15XX 163 default y if ARCH_OMAP15XX 164 select CPU_32v4T 165 select CPU_ABRT_EV4T 166 select CPU_PABRT_NOIFAR 167 select CPU_CACHE_V4WT 168 select CPU_CACHE_VIVT 169 select CPU_CP15_MMU 170 select CPU_COPY_V4WB if MMU 171 select CPU_TLB_V4WBI if MMU 172 help 173 The ARM925T is a mix between the ARM920T and ARM926T, but with 174 different instruction and data caches. It is used in TI's OMAP 175 device family. 176 177 Say Y if you want support for the ARM925T processor. 178 Otherwise, say N. 179 180# ARM926T 181config CPU_ARM926T 182 bool "Support ARM926T processor" 183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI 184 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI 185 select CPU_32v5 186 select CPU_ABRT_EV5TJ 187 select CPU_PABRT_NOIFAR 188 select CPU_CACHE_VIVT 189 select CPU_CP15_MMU 190 select CPU_COPY_V4WB if MMU 191 select CPU_TLB_V4WBI if MMU 192 help 193 This is a variant of the ARM920. It has slightly different 194 instruction sequences for cache and TLB operations. Curiously, 195 there is no documentation on it at the ARM corporate website. 196 197 Say Y if you want support for the ARM926T processor. 198 Otherwise, say N. 199 200# ARM940T 201config CPU_ARM940T 202 bool "Support ARM940T processor" if ARCH_INTEGRATOR 203 depends on !MMU 204 select CPU_32v4T 205 select CPU_ABRT_NOMMU 206 select CPU_PABRT_NOIFAR 207 select CPU_CACHE_VIVT 208 select CPU_CP15_MPU 209 help 210 ARM940T is a member of the ARM9TDMI family of general- 211 purpose microprocessors with MPU and separate 4KB 212 instruction and 4KB data cases, each with a 4-word line 213 length. 214 215 Say Y if you want support for the ARM940T processor. 216 Otherwise, say N. 217 218# ARM946E-S 219config CPU_ARM946E 220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 221 depends on !MMU 222 select CPU_32v5 223 select CPU_ABRT_NOMMU 224 select CPU_PABRT_NOIFAR 225 select CPU_CACHE_VIVT 226 select CPU_CP15_MPU 227 help 228 ARM946E-S is a member of the ARM9E-S family of high- 229 performance, 32-bit system-on-chip processor solutions. 230 The TCM and ARMv5TE 32-bit instruction set is supported. 231 232 Say Y if you want support for the ARM946E-S processor. 233 Otherwise, say N. 234 235# ARM1020 - needs validating 236config CPU_ARM1020 237 bool "Support ARM1020T (rev 0) processor" 238 depends on ARCH_INTEGRATOR 239 select CPU_32v5 240 select CPU_ABRT_EV4T 241 select CPU_PABRT_NOIFAR 242 select CPU_CACHE_V4WT 243 select CPU_CACHE_VIVT 244 select CPU_CP15_MMU 245 select CPU_COPY_V4WB if MMU 246 select CPU_TLB_V4WBI if MMU 247 help 248 The ARM1020 is the 32K cached version of the ARM10 processor, 249 with an addition of a floating-point unit. 250 251 Say Y if you want support for the ARM1020 processor. 252 Otherwise, say N. 253 254# ARM1020E - needs validating 255config CPU_ARM1020E 256 bool "Support ARM1020E processor" 257 depends on ARCH_INTEGRATOR 258 select CPU_32v5 259 select CPU_ABRT_EV4T 260 select CPU_PABRT_NOIFAR 261 select CPU_CACHE_V4WT 262 select CPU_CACHE_VIVT 263 select CPU_CP15_MMU 264 select CPU_COPY_V4WB if MMU 265 select CPU_TLB_V4WBI if MMU 266 depends on n 267 268# ARM1022E 269config CPU_ARM1022 270 bool "Support ARM1022E processor" 271 depends on ARCH_INTEGRATOR 272 select CPU_32v5 273 select CPU_ABRT_EV4T 274 select CPU_PABRT_NOIFAR 275 select CPU_CACHE_VIVT 276 select CPU_CP15_MMU 277 select CPU_COPY_V4WB if MMU # can probably do better 278 select CPU_TLB_V4WBI if MMU 279 help 280 The ARM1022E is an implementation of the ARMv5TE architecture 281 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 282 embedded trace macrocell, and a floating-point unit. 283 284 Say Y if you want support for the ARM1022E processor. 285 Otherwise, say N. 286 287# ARM1026EJ-S 288config CPU_ARM1026 289 bool "Support ARM1026EJ-S processor" 290 depends on ARCH_INTEGRATOR 291 select CPU_32v5 292 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 293 select CPU_PABRT_NOIFAR 294 select CPU_CACHE_VIVT 295 select CPU_CP15_MMU 296 select CPU_COPY_V4WB if MMU # can probably do better 297 select CPU_TLB_V4WBI if MMU 298 help 299 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 300 based upon the ARM10 integer core. 301 302 Say Y if you want support for the ARM1026EJ-S processor. 303 Otherwise, say N. 304 305# SA110 306config CPU_SA110 307 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC 308 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI 309 select CPU_32v3 if ARCH_RPC 310 select CPU_32v4 if !ARCH_RPC 311 select CPU_ABRT_EV4 312 select CPU_PABRT_NOIFAR 313 select CPU_CACHE_V4WB 314 select CPU_CACHE_VIVT 315 select CPU_CP15_MMU 316 select CPU_COPY_V4WB if MMU 317 select CPU_TLB_V4WB if MMU 318 help 319 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 320 is available at five speeds ranging from 100 MHz to 233 MHz. 321 More information is available at 322 <http://developer.intel.com/design/strong/sa110.htm>. 323 324 Say Y if you want support for the SA-110 processor. 325 Otherwise, say N. 326 327# SA1100 328config CPU_SA1100 329 bool 330 depends on ARCH_SA1100 331 default y 332 select CPU_32v4 333 select CPU_ABRT_EV4 334 select CPU_PABRT_NOIFAR 335 select CPU_CACHE_V4WB 336 select CPU_CACHE_VIVT 337 select CPU_CP15_MMU 338 select CPU_TLB_V4WB if MMU 339 340# XScale 341config CPU_XSCALE 342 bool 343 depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000 344 default y 345 select CPU_32v5 346 select CPU_ABRT_EV5T 347 select CPU_PABRT_NOIFAR 348 select CPU_CACHE_VIVT 349 select CPU_CP15_MMU 350 select CPU_TLB_V4WBI if MMU 351 352# XScale Core Version 3 353config CPU_XSC3 354 bool 355 depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx 356 default y 357 select CPU_32v5 358 select CPU_ABRT_EV5T 359 select CPU_PABRT_NOIFAR 360 select CPU_CACHE_VIVT 361 select CPU_CP15_MMU 362 select CPU_TLB_V4WBI if MMU 363 select IO_36 364 365# Feroceon 366config CPU_FEROCEON 367 bool 368 depends on ARCH_ORION5X 369 default y 370 select CPU_32v5 371 select CPU_ABRT_EV5T 372 select CPU_PABRT_NOIFAR 373 select CPU_CACHE_VIVT 374 select CPU_CP15_MMU 375 select CPU_COPY_V4WB if MMU 376 select CPU_TLB_V4WBI if MMU 377 378config CPU_FEROCEON_OLD_ID 379 bool "Accept early Feroceon cores with an ARM926 ID" 380 depends on CPU_FEROCEON && !CPU_ARM926T 381 default y 382 help 383 This enables the usage of some old Feroceon cores 384 for which the CPU ID is equal to the ARM926 ID. 385 Relevant for Feroceon-1850 and early Feroceon-2850. 386 387# ARMv6 388config CPU_V6 389 bool "Support ARM V6 processor" 390 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 391 default y if ARCH_MX3 392 default y if ARCH_MSM7X00A 393 select CPU_32v6 394 select CPU_ABRT_EV6 395 select CPU_PABRT_NOIFAR 396 select CPU_CACHE_V6 397 select CPU_CACHE_VIPT 398 select CPU_CP15_MMU 399 select CPU_HAS_ASID if MMU 400 select CPU_COPY_V6 if MMU 401 select CPU_TLB_V6 if MMU 402 403# ARMv6k 404config CPU_32v6K 405 bool "Support ARM V6K processor extensions" if !SMP 406 depends on CPU_V6 407 default y if SMP && !ARCH_MX3 408 help 409 Say Y here if your ARMv6 processor supports the 'K' extension. 410 This enables the kernel to use some instructions not present 411 on previous processors, and as such a kernel build with this 412 enabled will not boot on processors with do not support these 413 instructions. 414 415# ARMv7 416config CPU_V7 417 bool "Support ARM V7 processor" 418 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB 419 select CPU_32v6K 420 select CPU_32v7 421 select CPU_ABRT_EV7 422 select CPU_PABRT_IFAR 423 select CPU_CACHE_V7 424 select CPU_CACHE_VIPT 425 select CPU_CP15_MMU 426 select CPU_HAS_ASID if MMU 427 select CPU_COPY_V6 if MMU 428 select CPU_TLB_V7 if MMU 429 430# Figure out what processor architecture version we should be using. 431# This defines the compiler instruction set which depends on the machine type. 432config CPU_32v3 433 bool 434 select TLS_REG_EMUL if SMP || !MMU 435 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 436 437config CPU_32v4 438 bool 439 select TLS_REG_EMUL if SMP || !MMU 440 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 441 442config CPU_32v4T 443 bool 444 select TLS_REG_EMUL if SMP || !MMU 445 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 446 447config CPU_32v5 448 bool 449 select TLS_REG_EMUL if SMP || !MMU 450 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 451 452config CPU_32v6 453 bool 454 select TLS_REG_EMUL if !CPU_32v6K && !MMU 455 456config CPU_32v7 457 bool 458 459# The abort model 460config CPU_ABRT_NOMMU 461 bool 462 463config CPU_ABRT_EV4 464 bool 465 466config CPU_ABRT_EV4T 467 bool 468 469config CPU_ABRT_LV4T 470 bool 471 472config CPU_ABRT_EV5T 473 bool 474 475config CPU_ABRT_EV5TJ 476 bool 477 478config CPU_ABRT_EV6 479 bool 480 481config CPU_ABRT_EV7 482 bool 483 484config CPU_PABRT_IFAR 485 bool 486 487config CPU_PABRT_NOIFAR 488 bool 489 490# The cache model 491config CPU_CACHE_V3 492 bool 493 494config CPU_CACHE_V4 495 bool 496 497config CPU_CACHE_V4WT 498 bool 499 500config CPU_CACHE_V4WB 501 bool 502 503config CPU_CACHE_V6 504 bool 505 506config CPU_CACHE_V7 507 bool 508 509config CPU_CACHE_VIVT 510 bool 511 512config CPU_CACHE_VIPT 513 bool 514 515if MMU 516# The copy-page model 517config CPU_COPY_V3 518 bool 519 520config CPU_COPY_V4WT 521 bool 522 523config CPU_COPY_V4WB 524 bool 525 526config CPU_COPY_V6 527 bool 528 529# This selects the TLB model 530config CPU_TLB_V3 531 bool 532 help 533 ARM Architecture Version 3 TLB. 534 535config CPU_TLB_V4WT 536 bool 537 help 538 ARM Architecture Version 4 TLB with writethrough cache. 539 540config CPU_TLB_V4WB 541 bool 542 help 543 ARM Architecture Version 4 TLB with writeback cache. 544 545config CPU_TLB_V4WBI 546 bool 547 help 548 ARM Architecture Version 4 TLB with writeback cache and invalidate 549 instruction cache entry. 550 551config CPU_TLB_V6 552 bool 553 554config CPU_TLB_V7 555 bool 556 557endif 558 559config CPU_HAS_ASID 560 bool 561 help 562 This indicates whether the CPU has the ASID register; used to 563 tag TLB and possibly cache entries. 564 565config CPU_CP15 566 bool 567 help 568 Processor has the CP15 register. 569 570config CPU_CP15_MMU 571 bool 572 select CPU_CP15 573 help 574 Processor has the CP15 register, which has MMU related registers. 575 576config CPU_CP15_MPU 577 bool 578 select CPU_CP15 579 help 580 Processor has the CP15 register, which has MPU related registers. 581 582# 583# CPU supports 36-bit I/O 584# 585config IO_36 586 bool 587 588comment "Processor Features" 589 590config ARM_THUMB 591 bool "Support Thumb user binaries" 592 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON 593 default y 594 help 595 Say Y if you want to include kernel support for running user space 596 Thumb binaries. 597 598 The Thumb instruction set is a compressed form of the standard ARM 599 instruction set resulting in smaller binaries at the expense of 600 slightly less efficient code. 601 602 If you don't know what this all is, saying Y is a safe choice. 603 604config ARM_THUMBEE 605 bool "Enable ThumbEE CPU extension" 606 depends on CPU_V7 607 help 608 Say Y here if you have a CPU with the ThumbEE extension and code to 609 make use of it. Say N for code that can run on CPUs without ThumbEE. 610 611config CPU_BIG_ENDIAN 612 bool "Build big-endian kernel" 613 depends on ARCH_SUPPORTS_BIG_ENDIAN 614 help 615 Say Y if you plan on running a kernel in big-endian mode. 616 Note that your board must be properly built and your board 617 port must properly enable any big-endian related features 618 of your chipset/board/processor. 619 620config CPU_HIGH_VECTOR 621 depends on !MMU && CPU_CP15 && !CPU_ARM740T 622 bool "Select the High exception vector" 623 default n 624 help 625 Say Y here to select high exception vector(0xFFFF0000~). 626 The exception vector can be vary depending on the platform 627 design in nommu mode. If your platform needs to select 628 high exception vector, say Y. 629 Otherwise or if you are unsure, say N, and the low exception 630 vector (0x00000000~) will be used. 631 632config CPU_ICACHE_DISABLE 633 bool "Disable I-Cache (I-bit)" 634 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 635 help 636 Say Y here to disable the processor instruction cache. Unless 637 you have a reason not to or are unsure, say N. 638 639config CPU_DCACHE_DISABLE 640 bool "Disable D-Cache (C-bit)" 641 depends on CPU_CP15 642 help 643 Say Y here to disable the processor data cache. Unless 644 you have a reason not to or are unsure, say N. 645 646config CPU_DCACHE_SIZE 647 hex 648 depends on CPU_ARM740T || CPU_ARM946E 649 default 0x00001000 if CPU_ARM740T 650 default 0x00002000 # default size for ARM946E-S 651 help 652 Some cores are synthesizable to have various sized cache. For 653 ARM946E-S case, it can vary from 0KB to 1MB. 654 To support such cache operations, it is efficient to know the size 655 before compile time. 656 If your SoC is configured to have a different size, define the value 657 here with proper conditions. 658 659config CPU_DCACHE_WRITETHROUGH 660 bool "Force write through D-cache" 661 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE 662 default y if CPU_ARM925T 663 help 664 Say Y here to use the data cache in writethrough mode. Unless you 665 specifically require this or are unsure, say N. 666 667config CPU_CACHE_ROUND_ROBIN 668 bool "Round robin I and D cache replacement algorithm" 669 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 670 help 671 Say Y here to use the predictable round-robin cache replacement 672 policy. Unless you specifically require this or are unsure, say N. 673 674config CPU_BPREDICT_DISABLE 675 bool "Disable branch prediction" 676 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 677 help 678 Say Y here to disable branch prediction. If unsure, say N. 679 680config TLS_REG_EMUL 681 bool 682 help 683 An SMP system using a pre-ARMv6 processor (there are apparently 684 a few prototypes like that in existence) and therefore access to 685 that required register must be emulated. 686 687config HAS_TLS_REG 688 bool 689 depends on !TLS_REG_EMUL 690 default y if SMP || CPU_32v7 691 help 692 This selects support for the CP15 thread register. 693 It is defined to be available on some ARMv6 processors (including 694 all SMP capable ARMv6's) or later processors. User space may 695 assume directly accessing that register and always obtain the 696 expected value only on ARMv7 and above. 697 698config NEEDS_SYSCALL_FOR_CMPXCHG 699 bool 700 help 701 SMP on a pre-ARMv6 processor? Well OK then. 702 Forget about fast user space cmpxchg support. 703 It is just not possible. 704 705config OUTER_CACHE 706 bool 707 default n 708 709config CACHE_L2X0 710 bool "Enable the L2x0 outer cache controller" 711 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 712 default y 713 select OUTER_CACHE 714 help 715 This option enables the L2x0 PrimeCell. 716