1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM7TDMI 8config CPU_ARM7TDMI 9 bool 10 depends on !MMU 11 select CPU_32v4T 12 select CPU_ABRT_LV4T 13 select CPU_CACHE_V4 14 select CPU_PABRT_LEGACY 15 help 16 A 32-bit RISC microprocessor based on the ARM7 processor core 17 which has no memory control unit and cache. 18 19 Say Y if you want support for the ARM7TDMI processor. 20 Otherwise, say N. 21 22# ARM720T 23config CPU_ARM720T 24 bool 25 select CPU_32v4T 26 select CPU_ABRT_LV4T 27 select CPU_CACHE_V4 28 select CPU_CACHE_VIVT 29 select CPU_COPY_V4WT if MMU 30 select CPU_CP15_MMU 31 select CPU_PABRT_LEGACY 32 select CPU_TLB_V4WT if MMU 33 help 34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 35 MMU built around an ARM7TDMI core. 36 37 Say Y if you want support for the ARM720T processor. 38 Otherwise, say N. 39 40# ARM740T 41config CPU_ARM740T 42 bool 43 depends on !MMU 44 select CPU_32v4T 45 select CPU_ABRT_LV4T 46 select CPU_CACHE_V4 47 select CPU_CP15_MPU 48 select CPU_PABRT_LEGACY 49 help 50 A 32-bit RISC processor with 8KB cache or 4KB variants, 51 write buffer and MPU(Protection Unit) built around 52 an ARM7TDMI core. 53 54 Say Y if you want support for the ARM740T processor. 55 Otherwise, say N. 56 57# ARM9TDMI 58config CPU_ARM9TDMI 59 bool 60 depends on !MMU 61 select CPU_32v4T 62 select CPU_ABRT_NOMMU 63 select CPU_CACHE_V4 64 select CPU_PABRT_LEGACY 65 help 66 A 32-bit RISC microprocessor based on the ARM9 processor core 67 which has no memory control unit and cache. 68 69 Say Y if you want support for the ARM9TDMI processor. 70 Otherwise, say N. 71 72# ARM920T 73config CPU_ARM920T 74 bool 75 select CPU_32v4T 76 select CPU_ABRT_EV4T 77 select CPU_CACHE_V4WT 78 select CPU_CACHE_VIVT 79 select CPU_COPY_V4WB if MMU 80 select CPU_CP15_MMU 81 select CPU_PABRT_LEGACY 82 select CPU_TLB_V4WBI if MMU 83 help 84 The ARM920T is licensed to be produced by numerous vendors, 85 and is used in the Cirrus EP93xx and the Samsung S3C2410. 86 87 Say Y if you want support for the ARM920T processor. 88 Otherwise, say N. 89 90# ARM922T 91config CPU_ARM922T 92 bool 93 select CPU_32v4T 94 select CPU_ABRT_EV4T 95 select CPU_CACHE_V4WT 96 select CPU_CACHE_VIVT 97 select CPU_COPY_V4WB if MMU 98 select CPU_CP15_MMU 99 select CPU_PABRT_LEGACY 100 select CPU_TLB_V4WBI if MMU 101 help 102 The ARM922T is a version of the ARM920T, but with smaller 103 instruction and data caches. It is used in Altera's 104 Excalibur XA device family and Micrel's KS8695 Centaur. 105 106 Say Y if you want support for the ARM922T processor. 107 Otherwise, say N. 108 109# ARM925T 110config CPU_ARM925T 111 bool 112 select CPU_32v4T 113 select CPU_ABRT_EV4T 114 select CPU_CACHE_V4WT 115 select CPU_CACHE_VIVT 116 select CPU_COPY_V4WB if MMU 117 select CPU_CP15_MMU 118 select CPU_PABRT_LEGACY 119 select CPU_TLB_V4WBI if MMU 120 help 121 The ARM925T is a mix between the ARM920T and ARM926T, but with 122 different instruction and data caches. It is used in TI's OMAP 123 device family. 124 125 Say Y if you want support for the ARM925T processor. 126 Otherwise, say N. 127 128# ARM926T 129config CPU_ARM926T 130 bool 131 select CPU_32v5 132 select CPU_ABRT_EV5TJ 133 select CPU_CACHE_VIVT 134 select CPU_COPY_V4WB if MMU 135 select CPU_CP15_MMU 136 select CPU_PABRT_LEGACY 137 select CPU_TLB_V4WBI if MMU 138 help 139 This is a variant of the ARM920. It has slightly different 140 instruction sequences for cache and TLB operations. Curiously, 141 there is no documentation on it at the ARM corporate website. 142 143 Say Y if you want support for the ARM926T processor. 144 Otherwise, say N. 145 146# FA526 147config CPU_FA526 148 bool 149 select CPU_32v4 150 select CPU_ABRT_EV4 151 select CPU_CACHE_FA 152 select CPU_CACHE_VIVT 153 select CPU_COPY_FA if MMU 154 select CPU_CP15_MMU 155 select CPU_PABRT_LEGACY 156 select CPU_TLB_FA if MMU 157 help 158 The FA526 is a version of the ARMv4 compatible processor with 159 Branch Target Buffer, Unified TLB and cache line size 16. 160 161 Say Y if you want support for the FA526 processor. 162 Otherwise, say N. 163 164# ARM940T 165config CPU_ARM940T 166 bool 167 depends on !MMU 168 select CPU_32v4T 169 select CPU_ABRT_NOMMU 170 select CPU_CACHE_VIVT 171 select CPU_CP15_MPU 172 select CPU_PABRT_LEGACY 173 help 174 ARM940T is a member of the ARM9TDMI family of general- 175 purpose microprocessors with MPU and separate 4KB 176 instruction and 4KB data cases, each with a 4-word line 177 length. 178 179 Say Y if you want support for the ARM940T processor. 180 Otherwise, say N. 181 182# ARM946E-S 183config CPU_ARM946E 184 bool 185 depends on !MMU 186 select CPU_32v5 187 select CPU_ABRT_NOMMU 188 select CPU_CACHE_VIVT 189 select CPU_CP15_MPU 190 select CPU_PABRT_LEGACY 191 help 192 ARM946E-S is a member of the ARM9E-S family of high- 193 performance, 32-bit system-on-chip processor solutions. 194 The TCM and ARMv5TE 32-bit instruction set is supported. 195 196 Say Y if you want support for the ARM946E-S processor. 197 Otherwise, say N. 198 199# ARM1020 - needs validating 200config CPU_ARM1020 201 bool 202 select CPU_32v5 203 select CPU_ABRT_EV4T 204 select CPU_CACHE_V4WT 205 select CPU_CACHE_VIVT 206 select CPU_COPY_V4WB if MMU 207 select CPU_CP15_MMU 208 select CPU_PABRT_LEGACY 209 select CPU_TLB_V4WBI if MMU 210 help 211 The ARM1020 is the 32K cached version of the ARM10 processor, 212 with an addition of a floating-point unit. 213 214 Say Y if you want support for the ARM1020 processor. 215 Otherwise, say N. 216 217# ARM1020E - needs validating 218config CPU_ARM1020E 219 bool 220 depends on n 221 select CPU_32v5 222 select CPU_ABRT_EV4T 223 select CPU_CACHE_V4WT 224 select CPU_CACHE_VIVT 225 select CPU_COPY_V4WB if MMU 226 select CPU_CP15_MMU 227 select CPU_PABRT_LEGACY 228 select CPU_TLB_V4WBI if MMU 229 230# ARM1022E 231config CPU_ARM1022 232 bool 233 select CPU_32v5 234 select CPU_ABRT_EV4T 235 select CPU_CACHE_VIVT 236 select CPU_COPY_V4WB if MMU # can probably do better 237 select CPU_CP15_MMU 238 select CPU_PABRT_LEGACY 239 select CPU_TLB_V4WBI if MMU 240 help 241 The ARM1022E is an implementation of the ARMv5TE architecture 242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 243 embedded trace macrocell, and a floating-point unit. 244 245 Say Y if you want support for the ARM1022E processor. 246 Otherwise, say N. 247 248# ARM1026EJ-S 249config CPU_ARM1026 250 bool 251 select CPU_32v5 252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 253 select CPU_CACHE_VIVT 254 select CPU_COPY_V4WB if MMU # can probably do better 255 select CPU_CP15_MMU 256 select CPU_PABRT_LEGACY 257 select CPU_TLB_V4WBI if MMU 258 help 259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 260 based upon the ARM10 integer core. 261 262 Say Y if you want support for the ARM1026EJ-S processor. 263 Otherwise, say N. 264 265# SA110 266config CPU_SA110 267 bool 268 select CPU_32v3 if ARCH_RPC 269 select CPU_32v4 if !ARCH_RPC 270 select CPU_ABRT_EV4 271 select CPU_CACHE_V4WB 272 select CPU_CACHE_VIVT 273 select CPU_COPY_V4WB if MMU 274 select CPU_CP15_MMU 275 select CPU_PABRT_LEGACY 276 select CPU_TLB_V4WB if MMU 277 help 278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 279 is available at five speeds ranging from 100 MHz to 233 MHz. 280 More information is available at 281 <http://developer.intel.com/design/strong/sa110.htm>. 282 283 Say Y if you want support for the SA-110 processor. 284 Otherwise, say N. 285 286# SA1100 287config CPU_SA1100 288 bool 289 select CPU_32v4 290 select CPU_ABRT_EV4 291 select CPU_CACHE_V4WB 292 select CPU_CACHE_VIVT 293 select CPU_CP15_MMU 294 select CPU_PABRT_LEGACY 295 select CPU_TLB_V4WB if MMU 296 297# XScale 298config CPU_XSCALE 299 bool 300 select CPU_32v5 301 select CPU_ABRT_EV5T 302 select CPU_CACHE_VIVT 303 select CPU_CP15_MMU 304 select CPU_PABRT_LEGACY 305 select CPU_TLB_V4WBI if MMU 306 307# XScale Core Version 3 308config CPU_XSC3 309 bool 310 select CPU_32v5 311 select CPU_ABRT_EV5T 312 select CPU_CACHE_VIVT 313 select CPU_CP15_MMU 314 select CPU_PABRT_LEGACY 315 select CPU_TLB_V4WBI if MMU 316 select IO_36 317 318# Marvell PJ1 (Mohawk) 319config CPU_MOHAWK 320 bool 321 select CPU_32v5 322 select CPU_ABRT_EV5T 323 select CPU_CACHE_VIVT 324 select CPU_COPY_V4WB if MMU 325 select CPU_CP15_MMU 326 select CPU_PABRT_LEGACY 327 select CPU_TLB_V4WBI if MMU 328 329# Feroceon 330config CPU_FEROCEON 331 bool 332 select CPU_32v5 333 select CPU_ABRT_EV5T 334 select CPU_CACHE_VIVT 335 select CPU_COPY_FEROCEON if MMU 336 select CPU_CP15_MMU 337 select CPU_PABRT_LEGACY 338 select CPU_TLB_FEROCEON if MMU 339 340config CPU_FEROCEON_OLD_ID 341 bool "Accept early Feroceon cores with an ARM926 ID" 342 depends on CPU_FEROCEON && !CPU_ARM926T 343 default y 344 help 345 This enables the usage of some old Feroceon cores 346 for which the CPU ID is equal to the ARM926 ID. 347 Relevant for Feroceon-1850 and early Feroceon-2850. 348 349# Marvell PJ4 350config CPU_PJ4 351 bool 352 select ARM_THUMBEE 353 select CPU_V7 354 355config CPU_PJ4B 356 bool 357 select CPU_V7 358 359# ARMv6 360config CPU_V6 361 bool 362 select CPU_32v6 363 select CPU_ABRT_EV6 364 select CPU_CACHE_V6 365 select CPU_CACHE_VIPT 366 select CPU_COPY_V6 if MMU 367 select CPU_CP15_MMU 368 select CPU_HAS_ASID if MMU 369 select CPU_PABRT_V6 370 select CPU_TLB_V6 if MMU 371 372# ARMv6k 373config CPU_V6K 374 bool 375 select CPU_32v6 376 select CPU_32v6K 377 select CPU_ABRT_EV6 378 select CPU_CACHE_V6 379 select CPU_CACHE_VIPT 380 select CPU_COPY_V6 if MMU 381 select CPU_CP15_MMU 382 select CPU_HAS_ASID if MMU 383 select CPU_PABRT_V6 384 select CPU_TLB_V6 if MMU 385 386# ARMv7 387config CPU_V7 388 bool 389 select CPU_32v6K 390 select CPU_32v7 391 select CPU_ABRT_EV7 392 select CPU_CACHE_V7 393 select CPU_CACHE_VIPT 394 select CPU_COPY_V6 if MMU 395 select CPU_CP15_MMU if MMU 396 select CPU_CP15_MPU if !MMU 397 select CPU_HAS_ASID if MMU 398 select CPU_PABRT_V7 399 select CPU_TLB_V7 if MMU 400 401# ARMv7M 402config CPU_V7M 403 bool 404 select CPU_32v7M 405 select CPU_ABRT_NOMMU 406 select CPU_CACHE_NOP 407 select CPU_PABRT_LEGACY 408 select CPU_THUMBONLY 409 410config CPU_THUMBONLY 411 bool 412 # There are no CPUs available with MMU that don't implement an ARM ISA: 413 depends on !MMU 414 help 415 Select this if your CPU doesn't support the 32 bit ARM instructions. 416 417# Figure out what processor architecture version we should be using. 418# This defines the compiler instruction set which depends on the machine type. 419config CPU_32v3 420 bool 421 select CPU_USE_DOMAINS if MMU 422 select NEED_KUSER_HELPERS 423 select TLS_REG_EMUL if SMP || !MMU 424 select CPU_NO_EFFICIENT_FFS 425 426config CPU_32v4 427 bool 428 select CPU_USE_DOMAINS if MMU 429 select NEED_KUSER_HELPERS 430 select TLS_REG_EMUL if SMP || !MMU 431 select CPU_NO_EFFICIENT_FFS 432 433config CPU_32v4T 434 bool 435 select CPU_USE_DOMAINS if MMU 436 select NEED_KUSER_HELPERS 437 select TLS_REG_EMUL if SMP || !MMU 438 select CPU_NO_EFFICIENT_FFS 439 440config CPU_32v5 441 bool 442 select CPU_USE_DOMAINS if MMU 443 select NEED_KUSER_HELPERS 444 select TLS_REG_EMUL if SMP || !MMU 445 446config CPU_32v6 447 bool 448 select TLS_REG_EMUL if !CPU_32v6K && !MMU 449 450config CPU_32v6K 451 bool 452 453config CPU_32v7 454 bool 455 456config CPU_32v7M 457 bool 458 459# The abort model 460config CPU_ABRT_NOMMU 461 bool 462 463config CPU_ABRT_EV4 464 bool 465 466config CPU_ABRT_EV4T 467 bool 468 469config CPU_ABRT_LV4T 470 bool 471 472config CPU_ABRT_EV5T 473 bool 474 475config CPU_ABRT_EV5TJ 476 bool 477 478config CPU_ABRT_EV6 479 bool 480 481config CPU_ABRT_EV7 482 bool 483 484config CPU_PABRT_LEGACY 485 bool 486 487config CPU_PABRT_V6 488 bool 489 490config CPU_PABRT_V7 491 bool 492 493# The cache model 494config CPU_CACHE_V4 495 bool 496 497config CPU_CACHE_V4WT 498 bool 499 500config CPU_CACHE_V4WB 501 bool 502 503config CPU_CACHE_V6 504 bool 505 506config CPU_CACHE_V7 507 bool 508 509config CPU_CACHE_NOP 510 bool 511 512config CPU_CACHE_VIVT 513 bool 514 515config CPU_CACHE_VIPT 516 bool 517 518config CPU_CACHE_FA 519 bool 520 521if MMU 522# The copy-page model 523config CPU_COPY_V4WT 524 bool 525 526config CPU_COPY_V4WB 527 bool 528 529config CPU_COPY_FEROCEON 530 bool 531 532config CPU_COPY_FA 533 bool 534 535config CPU_COPY_V6 536 bool 537 538# This selects the TLB model 539config CPU_TLB_V4WT 540 bool 541 help 542 ARM Architecture Version 4 TLB with writethrough cache. 543 544config CPU_TLB_V4WB 545 bool 546 help 547 ARM Architecture Version 4 TLB with writeback cache. 548 549config CPU_TLB_V4WBI 550 bool 551 help 552 ARM Architecture Version 4 TLB with writeback cache and invalidate 553 instruction cache entry. 554 555config CPU_TLB_FEROCEON 556 bool 557 help 558 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 559 560config CPU_TLB_FA 561 bool 562 help 563 Faraday ARM FA526 architecture, unified TLB with writeback cache 564 and invalidate instruction cache entry. Branch target buffer is 565 also supported. 566 567config CPU_TLB_V6 568 bool 569 570config CPU_TLB_V7 571 bool 572 573config VERIFY_PERMISSION_FAULT 574 bool 575endif 576 577config CPU_HAS_ASID 578 bool 579 help 580 This indicates whether the CPU has the ASID register; used to 581 tag TLB and possibly cache entries. 582 583config CPU_CP15 584 bool 585 help 586 Processor has the CP15 register. 587 588config CPU_CP15_MMU 589 bool 590 select CPU_CP15 591 help 592 Processor has the CP15 register, which has MMU related registers. 593 594config CPU_CP15_MPU 595 bool 596 select CPU_CP15 597 help 598 Processor has the CP15 register, which has MPU related registers. 599 600config CPU_USE_DOMAINS 601 bool 602 help 603 This option enables or disables the use of domain switching 604 via the set_fs() function. 605 606config CPU_V7M_NUM_IRQ 607 int "Number of external interrupts connected to the NVIC" 608 depends on CPU_V7M 609 default 90 if ARCH_STM32 610 default 38 if ARCH_EFM32 611 default 112 if SOC_VF610 612 default 240 613 help 614 This option indicates the number of interrupts connected to the NVIC. 615 The value can be larger than the real number of interrupts supported 616 by the system, but must not be lower. 617 The default value is 240, corresponding to the maximum number of 618 interrupts supported by the NVIC on Cortex-M family. 619 620 If unsure, keep default value. 621 622# 623# CPU supports 36-bit I/O 624# 625config IO_36 626 bool 627 628comment "Processor Features" 629 630config ARM_LPAE 631 bool "Support for the Large Physical Address Extension" 632 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ 633 !CPU_32v4 && !CPU_32v3 634 help 635 Say Y if you have an ARMv7 processor supporting the LPAE page 636 table format and you would like to access memory beyond the 637 4GB limit. The resulting kernel image will not run on 638 processors without the LPA extension. 639 640 If unsure, say N. 641 642config ARM_PV_FIXUP 643 def_bool y 644 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE 645 646config ARCH_PHYS_ADDR_T_64BIT 647 def_bool ARM_LPAE 648 649config ARCH_DMA_ADDR_T_64BIT 650 bool 651 652config ARM_THUMB 653 bool "Support Thumb user binaries" if !CPU_THUMBONLY 654 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \ 655 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \ 656 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 657 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \ 658 CPU_V7 || CPU_FEROCEON || CPU_V7M 659 default y 660 help 661 Say Y if you want to include kernel support for running user space 662 Thumb binaries. 663 664 The Thumb instruction set is a compressed form of the standard ARM 665 instruction set resulting in smaller binaries at the expense of 666 slightly less efficient code. 667 668 If you don't know what this all is, saying Y is a safe choice. 669 670config ARM_THUMBEE 671 bool "Enable ThumbEE CPU extension" 672 depends on CPU_V7 673 help 674 Say Y here if you have a CPU with the ThumbEE extension and code to 675 make use of it. Say N for code that can run on CPUs without ThumbEE. 676 677config ARM_VIRT_EXT 678 bool 679 depends on MMU 680 default y if CPU_V7 681 help 682 Enable the kernel to make use of the ARM Virtualization 683 Extensions to install hypervisors without run-time firmware 684 assistance. 685 686 A compliant bootloader is required in order to make maximum 687 use of this feature. Refer to Documentation/arm/Booting for 688 details. 689 690config SWP_EMULATE 691 bool "Emulate SWP/SWPB instructions" if !SMP 692 depends on CPU_V7 693 default y if SMP 694 select HAVE_PROC_CPU if PROC_FS 695 help 696 ARMv6 architecture deprecates use of the SWP/SWPB instructions. 697 ARMv7 multiprocessing extensions introduce the ability to disable 698 these instructions, triggering an undefined instruction exception 699 when executed. Say Y here to enable software emulation of these 700 instructions for userspace (not kernel) using LDREX/STREX. 701 Also creates /proc/cpu/swp_emulation for statistics. 702 703 In some older versions of glibc [<=2.8] SWP is used during futex 704 trylock() operations with the assumption that the code will not 705 be preempted. This invalid assumption may be more likely to fail 706 with SWP emulation enabled, leading to deadlock of the user 707 application. 708 709 NOTE: when accessing uncached shared regions, LDREX/STREX rely 710 on an external transaction monitoring block called a global 711 monitor to maintain update atomicity. If your system does not 712 implement a global monitor, this option can cause programs that 713 perform SWP operations to uncached memory to deadlock. 714 715 If unsure, say Y. 716 717config CPU_BIG_ENDIAN 718 bool "Build big-endian kernel" 719 depends on ARCH_SUPPORTS_BIG_ENDIAN 720 help 721 Say Y if you plan on running a kernel in big-endian mode. 722 Note that your board must be properly built and your board 723 port must properly enable any big-endian related features 724 of your chipset/board/processor. 725 726config CPU_ENDIAN_BE8 727 bool 728 depends on CPU_BIG_ENDIAN 729 default CPU_V6 || CPU_V6K || CPU_V7 730 help 731 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. 732 733config CPU_ENDIAN_BE32 734 bool 735 depends on CPU_BIG_ENDIAN 736 default !CPU_ENDIAN_BE8 737 help 738 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. 739 740config CPU_HIGH_VECTOR 741 depends on !MMU && CPU_CP15 && !CPU_ARM740T 742 bool "Select the High exception vector" 743 help 744 Say Y here to select high exception vector(0xFFFF0000~). 745 The exception vector can vary depending on the platform 746 design in nommu mode. If your platform needs to select 747 high exception vector, say Y. 748 Otherwise or if you are unsure, say N, and the low exception 749 vector (0x00000000~) will be used. 750 751config CPU_ICACHE_DISABLE 752 bool "Disable I-Cache (I-bit)" 753 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 754 help 755 Say Y here to disable the processor instruction cache. Unless 756 you have a reason not to or are unsure, say N. 757 758config CPU_DCACHE_DISABLE 759 bool "Disable D-Cache (C-bit)" 760 depends on CPU_CP15 && !SMP 761 help 762 Say Y here to disable the processor data cache. Unless 763 you have a reason not to or are unsure, say N. 764 765config CPU_DCACHE_SIZE 766 hex 767 depends on CPU_ARM740T || CPU_ARM946E 768 default 0x00001000 if CPU_ARM740T 769 default 0x00002000 # default size for ARM946E-S 770 help 771 Some cores are synthesizable to have various sized cache. For 772 ARM946E-S case, it can vary from 0KB to 1MB. 773 To support such cache operations, it is efficient to know the size 774 before compile time. 775 If your SoC is configured to have a different size, define the value 776 here with proper conditions. 777 778config CPU_DCACHE_WRITETHROUGH 779 bool "Force write through D-cache" 780 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE 781 default y if CPU_ARM925T 782 help 783 Say Y here to use the data cache in writethrough mode. Unless you 784 specifically require this or are unsure, say N. 785 786config CPU_CACHE_ROUND_ROBIN 787 bool "Round robin I and D cache replacement algorithm" 788 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 789 help 790 Say Y here to use the predictable round-robin cache replacement 791 policy. Unless you specifically require this or are unsure, say N. 792 793config CPU_BPREDICT_DISABLE 794 bool "Disable branch prediction" 795 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 796 help 797 Say Y here to disable branch prediction. If unsure, say N. 798 799config TLS_REG_EMUL 800 bool 801 select NEED_KUSER_HELPERS 802 help 803 An SMP system using a pre-ARMv6 processor (there are apparently 804 a few prototypes like that in existence) and therefore access to 805 that required register must be emulated. 806 807config NEED_KUSER_HELPERS 808 bool 809 810config KUSER_HELPERS 811 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS 812 depends on MMU 813 default y 814 help 815 Warning: disabling this option may break user programs. 816 817 Provide kuser helpers in the vector page. The kernel provides 818 helper code to userspace in read only form at a fixed location 819 in the high vector page to allow userspace to be independent of 820 the CPU type fitted to the system. This permits binaries to be 821 run on ARMv4 through to ARMv7 without modification. 822 823 See Documentation/arm/kernel_user_helpers.txt for details. 824 825 However, the fixed address nature of these helpers can be used 826 by ROP (return orientated programming) authors when creating 827 exploits. 828 829 If all of the binaries and libraries which run on your platform 830 are built specifically for your platform, and make no use of 831 these helpers, then you can turn this option off to hinder 832 such exploits. However, in that case, if a binary or library 833 relying on those helpers is run, it will receive a SIGILL signal, 834 which will terminate the program. 835 836 Say N here only if you are absolutely certain that you do not 837 need these helpers; otherwise, the safe option is to say Y. 838 839config VDSO 840 bool "Enable VDSO for acceleration of some system calls" 841 depends on AEABI && MMU && CPU_V7 842 default y if ARM_ARCH_TIMER 843 select GENERIC_TIME_VSYSCALL 844 help 845 Place in the process address space an ELF shared object 846 providing fast implementations of gettimeofday and 847 clock_gettime. Systems that implement the ARM architected 848 timer will receive maximum benefit. 849 850 You must have glibc 2.22 or later for programs to seamlessly 851 take advantage of this. 852 853config DMA_CACHE_RWFO 854 bool "Enable read/write for ownership DMA cache maintenance" 855 depends on CPU_V6K && SMP 856 default y 857 help 858 The Snoop Control Unit on ARM11MPCore does not detect the 859 cache maintenance operations and the dma_{map,unmap}_area() 860 functions may leave stale cache entries on other CPUs. By 861 enabling this option, Read or Write For Ownership in the ARMv6 862 DMA cache maintenance functions is performed. These LDR/STR 863 instructions change the cache line state to shared or modified 864 so that the cache operation has the desired effect. 865 866 Note that the workaround is only valid on processors that do 867 not perform speculative loads into the D-cache. For such 868 processors, if cache maintenance operations are not broadcast 869 in hardware, other workarounds are needed (e.g. cache 870 maintenance broadcasting in software via FIQ). 871 872config OUTER_CACHE 873 bool 874 875config OUTER_CACHE_SYNC 876 bool 877 select ARM_HEAVY_MB 878 help 879 The outer cache has a outer_cache_fns.sync function pointer 880 that can be used to drain the write buffer of the outer cache. 881 882config CACHE_FEROCEON_L2 883 bool "Enable the Feroceon L2 cache controller" 884 depends on ARCH_MV78XX0 || ARCH_MVEBU 885 default y 886 select OUTER_CACHE 887 help 888 This option enables the Feroceon L2 cache controller. 889 890config CACHE_FEROCEON_L2_WRITETHROUGH 891 bool "Force Feroceon L2 cache write through" 892 depends on CACHE_FEROCEON_L2 893 help 894 Say Y here to use the Feroceon L2 cache in writethrough mode. 895 Unless you specifically require this, say N for writeback mode. 896 897config MIGHT_HAVE_CACHE_L2X0 898 bool 899 help 900 This option should be selected by machines which have a L2x0 901 or PL310 cache controller, but where its use is optional. 902 903 The only effect of this option is to make CACHE_L2X0 and 904 related options available to the user for configuration. 905 906 Boards or SoCs which always require the cache controller 907 support to be present should select CACHE_L2X0 directly 908 instead of this option, thus preventing the user from 909 inadvertently configuring a broken kernel. 910 911config CACHE_L2X0 912 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 913 default MIGHT_HAVE_CACHE_L2X0 914 select OUTER_CACHE 915 select OUTER_CACHE_SYNC 916 help 917 This option enables the L2x0 PrimeCell. 918 919if CACHE_L2X0 920 921config PL310_ERRATA_588369 922 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 923 help 924 The PL310 L2 cache controller implements three types of Clean & 925 Invalidate maintenance operations: by Physical Address 926 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 927 They are architecturally defined to behave as the execution of a 928 clean operation followed immediately by an invalidate operation, 929 both performing to the same memory location. This functionality 930 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0) 931 as clean lines are not invalidated as a result of these operations. 932 933config PL310_ERRATA_727915 934 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 935 help 936 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 937 operation (offset 0x7FC). This operation runs in background so that 938 PL310 can handle normal accesses while it is in progress. Under very 939 rare circumstances, due to this erratum, write data can be lost when 940 PL310 treats a cacheable write transaction during a Clean & 941 Invalidate by Way operation. Revisions prior to r3p1 are affected by 942 this errata (fixed in r3p1). 943 944config PL310_ERRATA_753970 945 bool "PL310 errata: cache sync operation may be faulty" 946 help 947 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 948 949 Under some condition the effect of cache sync operation on 950 the store buffer still remains when the operation completes. 951 This means that the store buffer is always asked to drain and 952 this prevents it from merging any further writes. The workaround 953 is to replace the normal offset of cache sync operation (0x730) 954 by another offset targeting an unmapped PL310 register 0x740. 955 This has the same effect as the cache sync operation: store buffer 956 drain and waiting for all buffers empty. 957 958config PL310_ERRATA_769419 959 bool "PL310 errata: no automatic Store Buffer drain" 960 help 961 On revisions of the PL310 prior to r3p2, the Store Buffer does 962 not automatically drain. This can cause normal, non-cacheable 963 writes to be retained when the memory system is idle, leading 964 to suboptimal I/O performance for drivers using coherent DMA. 965 This option adds a write barrier to the cpu_idle loop so that, 966 on systems with an outer cache, the store buffer is drained 967 explicitly. 968 969endif 970 971config CACHE_TAUROS2 972 bool "Enable the Tauros2 L2 cache controller" 973 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) 974 default y 975 select OUTER_CACHE 976 help 977 This option enables the Tauros2 L2 cache controller (as 978 found on PJ1/PJ4). 979 980config CACHE_UNIPHIER 981 bool "Enable the UniPhier outer cache controller" 982 depends on ARCH_UNIPHIER 983 default y 984 select OUTER_CACHE 985 select OUTER_CACHE_SYNC 986 help 987 This option enables the UniPhier outer cache (system cache) 988 controller. 989 990config CACHE_XSC3L2 991 bool "Enable the L2 cache on XScale3" 992 depends on CPU_XSC3 993 default y 994 select OUTER_CACHE 995 help 996 This option enables the L2 cache on XScale3. 997 998config ARM_L1_CACHE_SHIFT_6 999 bool 1000 default y if CPU_V7 1001 help 1002 Setting ARM L1 cache line size to 64 Bytes. 1003 1004config ARM_L1_CACHE_SHIFT 1005 int 1006 default 6 if ARM_L1_CACHE_SHIFT_6 1007 default 5 1008 1009config ARM_DMA_MEM_BUFFERABLE 1010 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 1011 default y if CPU_V6 || CPU_V6K || CPU_V7 1012 help 1013 Historically, the kernel has used strongly ordered mappings to 1014 provide DMA coherent memory. With the advent of ARMv7, mapping 1015 memory with differing types results in unpredictable behaviour, 1016 so on these CPUs, this option is forced on. 1017 1018 Multiple mappings with differing attributes is also unpredictable 1019 on ARMv6 CPUs, but since they do not have aggressive speculative 1020 prefetch, no harm appears to occur. 1021 1022 However, drivers may be missing the necessary barriers for ARMv6, 1023 and therefore turning this on may result in unpredictable driver 1024 behaviour. Therefore, we offer this as an option. 1025 1026 You are recommended say 'Y' here and debug any affected drivers. 1027 1028config ARCH_HAS_BARRIERS 1029 bool 1030 help 1031 This option allows the use of custom mandatory barriers 1032 included via the mach/barriers.h file. 1033 1034config ARM_HEAVY_MB 1035 bool 1036 1037config ARCH_SUPPORTS_BIG_ENDIAN 1038 bool 1039 help 1040 This option specifies the architecture can support big endian 1041 operation. 1042 1043config DEBUG_RODATA 1044 bool "Make kernel text and rodata read-only" 1045 depends on MMU && !XIP_KERNEL 1046 default y if CPU_V7 1047 help 1048 If this is set, kernel text and rodata memory will be made 1049 read-only, and non-text kernel memory will be made non-executable. 1050 The tradeoff is that each region is padded to section-size (1MiB) 1051 boundaries (because their permissions are different and splitting 1052 the 1M pages into 4K ones causes TLB performance problems), which 1053 can waste memory. 1054 1055config DEBUG_ALIGN_RODATA 1056 bool "Make rodata strictly non-executable" 1057 depends on DEBUG_RODATA 1058 default y 1059 help 1060 If this is set, rodata will be made explicitly non-executable. This 1061 provides protection on the rare chance that attackers might find and 1062 use ROP gadgets that exist in the rodata section. This adds an 1063 additional section-aligned split of rodata from kernel text so it 1064 can be made explicitly non-executable. This padding may waste memory 1065 space to gain the additional protection. 1066