1comment "Processor Type" 2 3config CPU_32 4 bool 5 default y 6 7# Select CPU types depending on the architecture selected. This selects 8# which CPUs we support in the kernel image, and the compiler instruction 9# optimiser behaviour. 10 11# ARM610 12config CPU_ARM610 13 bool "Support ARM610 processor" if ARCH_RPC 14 select CPU_32v3 15 select CPU_CACHE_V3 16 select CPU_CACHE_VIVT 17 select CPU_CP15_MMU 18 select CPU_COPY_V3 if MMU 19 select CPU_TLB_V3 if MMU 20 select CPU_PABRT_LEGACY 21 help 22 The ARM610 is the successor to the ARM3 processor 23 and was produced by VLSI Technology Inc. 24 25 Say Y if you want support for the ARM610 processor. 26 Otherwise, say N. 27 28# ARM7TDMI 29config CPU_ARM7TDMI 30 bool "Support ARM7TDMI processor" 31 depends on !MMU 32 select CPU_32v4T 33 select CPU_ABRT_LV4T 34 select CPU_PABRT_LEGACY 35 select CPU_CACHE_V4 36 help 37 A 32-bit RISC microprocessor based on the ARM7 processor core 38 which has no memory control unit and cache. 39 40 Say Y if you want support for the ARM7TDMI processor. 41 Otherwise, say N. 42 43# ARM710 44config CPU_ARM710 45 bool "Support ARM710 processor" if ARCH_RPC 46 select CPU_32v3 47 select CPU_CACHE_V3 48 select CPU_CACHE_VIVT 49 select CPU_CP15_MMU 50 select CPU_COPY_V3 if MMU 51 select CPU_TLB_V3 if MMU 52 select CPU_PABRT_LEGACY 53 help 54 A 32-bit RISC microprocessor based on the ARM7 processor core 55 designed by Advanced RISC Machines Ltd. The ARM710 is the 56 successor to the ARM610 processor. It was released in 57 July 1994 by VLSI Technology Inc. 58 59 Say Y if you want support for the ARM710 processor. 60 Otherwise, say N. 61 62# ARM720T 63config CPU_ARM720T 64 bool "Support ARM720T processor" if ARCH_INTEGRATOR 65 select CPU_32v4T 66 select CPU_ABRT_LV4T 67 select CPU_PABRT_LEGACY 68 select CPU_CACHE_V4 69 select CPU_CACHE_VIVT 70 select CPU_CP15_MMU 71 select CPU_COPY_V4WT if MMU 72 select CPU_TLB_V4WT if MMU 73 help 74 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 75 MMU built around an ARM7TDMI core. 76 77 Say Y if you want support for the ARM720T processor. 78 Otherwise, say N. 79 80# ARM740T 81config CPU_ARM740T 82 bool "Support ARM740T processor" if ARCH_INTEGRATOR 83 depends on !MMU 84 select CPU_32v4T 85 select CPU_ABRT_LV4T 86 select CPU_PABRT_LEGACY 87 select CPU_CACHE_V3 # although the core is v4t 88 select CPU_CP15_MPU 89 help 90 A 32-bit RISC processor with 8KB cache or 4KB variants, 91 write buffer and MPU(Protection Unit) built around 92 an ARM7TDMI core. 93 94 Say Y if you want support for the ARM740T processor. 95 Otherwise, say N. 96 97# ARM9TDMI 98config CPU_ARM9TDMI 99 bool "Support ARM9TDMI processor" 100 depends on !MMU 101 select CPU_32v4T 102 select CPU_ABRT_NOMMU 103 select CPU_PABRT_LEGACY 104 select CPU_CACHE_V4 105 help 106 A 32-bit RISC microprocessor based on the ARM9 processor core 107 which has no memory control unit and cache. 108 109 Say Y if you want support for the ARM9TDMI processor. 110 Otherwise, say N. 111 112# ARM920T 113config CPU_ARM920T 114 bool "Support ARM920T processor" if ARCH_INTEGRATOR 115 select CPU_32v4T 116 select CPU_ABRT_EV4T 117 select CPU_PABRT_LEGACY 118 select CPU_CACHE_V4WT 119 select CPU_CACHE_VIVT 120 select CPU_CP15_MMU 121 select CPU_COPY_V4WB if MMU 122 select CPU_TLB_V4WBI if MMU 123 help 124 The ARM920T is licensed to be produced by numerous vendors, 125 and is used in the Cirrus EP93xx and the Samsung S3C2410. 126 127 Say Y if you want support for the ARM920T processor. 128 Otherwise, say N. 129 130# ARM922T 131config CPU_ARM922T 132 bool "Support ARM922T processor" if ARCH_INTEGRATOR 133 select CPU_32v4T 134 select CPU_ABRT_EV4T 135 select CPU_PABRT_LEGACY 136 select CPU_CACHE_V4WT 137 select CPU_CACHE_VIVT 138 select CPU_CP15_MMU 139 select CPU_COPY_V4WB if MMU 140 select CPU_TLB_V4WBI if MMU 141 help 142 The ARM922T is a version of the ARM920T, but with smaller 143 instruction and data caches. It is used in Altera's 144 Excalibur XA device family and Micrel's KS8695 Centaur. 145 146 Say Y if you want support for the ARM922T processor. 147 Otherwise, say N. 148 149# ARM925T 150config CPU_ARM925T 151 bool "Support ARM925T processor" if ARCH_OMAP1 152 select CPU_32v4T 153 select CPU_ABRT_EV4T 154 select CPU_PABRT_LEGACY 155 select CPU_CACHE_V4WT 156 select CPU_CACHE_VIVT 157 select CPU_CP15_MMU 158 select CPU_COPY_V4WB if MMU 159 select CPU_TLB_V4WBI if MMU 160 help 161 The ARM925T is a mix between the ARM920T and ARM926T, but with 162 different instruction and data caches. It is used in TI's OMAP 163 device family. 164 165 Say Y if you want support for the ARM925T processor. 166 Otherwise, say N. 167 168# ARM926T 169config CPU_ARM926T 170 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 171 select CPU_32v5 172 select CPU_ABRT_EV5TJ 173 select CPU_PABRT_LEGACY 174 select CPU_CACHE_VIVT 175 select CPU_CP15_MMU 176 select CPU_COPY_V4WB if MMU 177 select CPU_TLB_V4WBI if MMU 178 help 179 This is a variant of the ARM920. It has slightly different 180 instruction sequences for cache and TLB operations. Curiously, 181 there is no documentation on it at the ARM corporate website. 182 183 Say Y if you want support for the ARM926T processor. 184 Otherwise, say N. 185 186# FA526 187config CPU_FA526 188 bool 189 select CPU_32v4 190 select CPU_ABRT_EV4 191 select CPU_PABRT_LEGACY 192 select CPU_CACHE_VIVT 193 select CPU_CP15_MMU 194 select CPU_CACHE_FA 195 select CPU_COPY_FA if MMU 196 select CPU_TLB_FA if MMU 197 help 198 The FA526 is a version of the ARMv4 compatible processor with 199 Branch Target Buffer, Unified TLB and cache line size 16. 200 201 Say Y if you want support for the FA526 processor. 202 Otherwise, say N. 203 204# ARM940T 205config CPU_ARM940T 206 bool "Support ARM940T processor" if ARCH_INTEGRATOR 207 depends on !MMU 208 select CPU_32v4T 209 select CPU_ABRT_NOMMU 210 select CPU_PABRT_LEGACY 211 select CPU_CACHE_VIVT 212 select CPU_CP15_MPU 213 help 214 ARM940T is a member of the ARM9TDMI family of general- 215 purpose microprocessors with MPU and separate 4KB 216 instruction and 4KB data cases, each with a 4-word line 217 length. 218 219 Say Y if you want support for the ARM940T processor. 220 Otherwise, say N. 221 222# ARM946E-S 223config CPU_ARM946E 224 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 225 depends on !MMU 226 select CPU_32v5 227 select CPU_ABRT_NOMMU 228 select CPU_PABRT_LEGACY 229 select CPU_CACHE_VIVT 230 select CPU_CP15_MPU 231 help 232 ARM946E-S is a member of the ARM9E-S family of high- 233 performance, 32-bit system-on-chip processor solutions. 234 The TCM and ARMv5TE 32-bit instruction set is supported. 235 236 Say Y if you want support for the ARM946E-S processor. 237 Otherwise, say N. 238 239# ARM1020 - needs validating 240config CPU_ARM1020 241 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 242 select CPU_32v5 243 select CPU_ABRT_EV4T 244 select CPU_PABRT_LEGACY 245 select CPU_CACHE_V4WT 246 select CPU_CACHE_VIVT 247 select CPU_CP15_MMU 248 select CPU_COPY_V4WB if MMU 249 select CPU_TLB_V4WBI if MMU 250 help 251 The ARM1020 is the 32K cached version of the ARM10 processor, 252 with an addition of a floating-point unit. 253 254 Say Y if you want support for the ARM1020 processor. 255 Otherwise, say N. 256 257# ARM1020E - needs validating 258config CPU_ARM1020E 259 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 260 select CPU_32v5 261 select CPU_ABRT_EV4T 262 select CPU_PABRT_LEGACY 263 select CPU_CACHE_V4WT 264 select CPU_CACHE_VIVT 265 select CPU_CP15_MMU 266 select CPU_COPY_V4WB if MMU 267 select CPU_TLB_V4WBI if MMU 268 depends on n 269 270# ARM1022E 271config CPU_ARM1022 272 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 273 select CPU_32v5 274 select CPU_ABRT_EV4T 275 select CPU_PABRT_LEGACY 276 select CPU_CACHE_VIVT 277 select CPU_CP15_MMU 278 select CPU_COPY_V4WB if MMU # can probably do better 279 select CPU_TLB_V4WBI if MMU 280 help 281 The ARM1022E is an implementation of the ARMv5TE architecture 282 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 283 embedded trace macrocell, and a floating-point unit. 284 285 Say Y if you want support for the ARM1022E processor. 286 Otherwise, say N. 287 288# ARM1026EJ-S 289config CPU_ARM1026 290 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 291 select CPU_32v5 292 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 293 select CPU_PABRT_LEGACY 294 select CPU_CACHE_VIVT 295 select CPU_CP15_MMU 296 select CPU_COPY_V4WB if MMU # can probably do better 297 select CPU_TLB_V4WBI if MMU 298 help 299 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 300 based upon the ARM10 integer core. 301 302 Say Y if you want support for the ARM1026EJ-S processor. 303 Otherwise, say N. 304 305# SA110 306config CPU_SA110 307 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC 308 select CPU_32v3 if ARCH_RPC 309 select CPU_32v4 if !ARCH_RPC 310 select CPU_ABRT_EV4 311 select CPU_PABRT_LEGACY 312 select CPU_CACHE_V4WB 313 select CPU_CACHE_VIVT 314 select CPU_CP15_MMU 315 select CPU_COPY_V4WB if MMU 316 select CPU_TLB_V4WB if MMU 317 help 318 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 319 is available at five speeds ranging from 100 MHz to 233 MHz. 320 More information is available at 321 <http://developer.intel.com/design/strong/sa110.htm>. 322 323 Say Y if you want support for the SA-110 processor. 324 Otherwise, say N. 325 326# SA1100 327config CPU_SA1100 328 bool 329 select CPU_32v4 330 select CPU_ABRT_EV4 331 select CPU_PABRT_LEGACY 332 select CPU_CACHE_V4WB 333 select CPU_CACHE_VIVT 334 select CPU_CP15_MMU 335 select CPU_TLB_V4WB if MMU 336 337# XScale 338config CPU_XSCALE 339 bool 340 select CPU_32v5 341 select CPU_ABRT_EV5T 342 select CPU_PABRT_LEGACY 343 select CPU_CACHE_VIVT 344 select CPU_CP15_MMU 345 select CPU_TLB_V4WBI if MMU 346 347# XScale Core Version 3 348config CPU_XSC3 349 bool 350 select CPU_32v5 351 select CPU_ABRT_EV5T 352 select CPU_PABRT_LEGACY 353 select CPU_CACHE_VIVT 354 select CPU_CP15_MMU 355 select CPU_TLB_V4WBI if MMU 356 select IO_36 357 358# Marvell PJ1 (Mohawk) 359config CPU_MOHAWK 360 bool 361 select CPU_32v5 362 select CPU_ABRT_EV5T 363 select CPU_PABRT_LEGACY 364 select CPU_CACHE_VIVT 365 select CPU_CP15_MMU 366 select CPU_TLB_V4WBI if MMU 367 select CPU_COPY_V4WB if MMU 368 369# Feroceon 370config CPU_FEROCEON 371 bool 372 select CPU_32v5 373 select CPU_ABRT_EV5T 374 select CPU_PABRT_LEGACY 375 select CPU_CACHE_VIVT 376 select CPU_CP15_MMU 377 select CPU_COPY_FEROCEON if MMU 378 select CPU_TLB_FEROCEON if MMU 379 380config CPU_FEROCEON_OLD_ID 381 bool "Accept early Feroceon cores with an ARM926 ID" 382 depends on CPU_FEROCEON && !CPU_ARM926T 383 default y 384 help 385 This enables the usage of some old Feroceon cores 386 for which the CPU ID is equal to the ARM926 ID. 387 Relevant for Feroceon-1850 and early Feroceon-2850. 388 389# ARMv6 390config CPU_V6 391 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 392 select CPU_32v6 393 select CPU_ABRT_EV6 394 select CPU_PABRT_V6 395 select CPU_CACHE_V6 396 select CPU_CACHE_VIPT 397 select CPU_CP15_MMU 398 select CPU_HAS_ASID if MMU 399 select CPU_COPY_V6 if MMU 400 select CPU_TLB_V6 if MMU 401 402# ARMv6k 403config CPU_32v6K 404 bool "Support ARM V6K processor extensions" if !SMP 405 depends on CPU_V6 406 default y if SMP && !ARCH_MX3 407 help 408 Say Y here if your ARMv6 processor supports the 'K' extension. 409 This enables the kernel to use some instructions not present 410 on previous processors, and as such a kernel build with this 411 enabled will not boot on processors with do not support these 412 instructions. 413 414# ARMv7 415config CPU_V7 416 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 417 select CPU_32v6K 418 select CPU_32v7 419 select CPU_ABRT_EV7 420 select CPU_PABRT_V7 421 select CPU_CACHE_V7 422 select CPU_CACHE_VIPT 423 select CPU_CP15_MMU 424 select CPU_HAS_ASID if MMU 425 select CPU_COPY_V6 if MMU 426 select CPU_TLB_V7 if MMU 427 428# Figure out what processor architecture version we should be using. 429# This defines the compiler instruction set which depends on the machine type. 430config CPU_32v3 431 bool 432 select TLS_REG_EMUL if SMP || !MMU 433 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 434 435config CPU_32v4 436 bool 437 select TLS_REG_EMUL if SMP || !MMU 438 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 439 440config CPU_32v4T 441 bool 442 select TLS_REG_EMUL if SMP || !MMU 443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 444 445config CPU_32v5 446 bool 447 select TLS_REG_EMUL if SMP || !MMU 448 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 449 450config CPU_32v6 451 bool 452 select TLS_REG_EMUL if !CPU_32v6K && !MMU 453 454config CPU_32v7 455 bool 456 457# The abort model 458config CPU_ABRT_NOMMU 459 bool 460 461config CPU_ABRT_EV4 462 bool 463 464config CPU_ABRT_EV4T 465 bool 466 467config CPU_ABRT_LV4T 468 bool 469 470config CPU_ABRT_EV5T 471 bool 472 473config CPU_ABRT_EV5TJ 474 bool 475 476config CPU_ABRT_EV6 477 bool 478 479config CPU_ABRT_EV7 480 bool 481 482config CPU_PABRT_LEGACY 483 bool 484 485config CPU_PABRT_V6 486 bool 487 488config CPU_PABRT_V7 489 bool 490 491# The cache model 492config CPU_CACHE_V3 493 bool 494 495config CPU_CACHE_V4 496 bool 497 498config CPU_CACHE_V4WT 499 bool 500 501config CPU_CACHE_V4WB 502 bool 503 504config CPU_CACHE_V6 505 bool 506 507config CPU_CACHE_V7 508 bool 509 510config CPU_CACHE_VIVT 511 bool 512 513config CPU_CACHE_VIPT 514 bool 515 516config CPU_CACHE_FA 517 bool 518 519if MMU 520# The copy-page model 521config CPU_COPY_V3 522 bool 523 524config CPU_COPY_V4WT 525 bool 526 527config CPU_COPY_V4WB 528 bool 529 530config CPU_COPY_FEROCEON 531 bool 532 533config CPU_COPY_FA 534 bool 535 536config CPU_COPY_V6 537 bool 538 539# This selects the TLB model 540config CPU_TLB_V3 541 bool 542 help 543 ARM Architecture Version 3 TLB. 544 545config CPU_TLB_V4WT 546 bool 547 help 548 ARM Architecture Version 4 TLB with writethrough cache. 549 550config CPU_TLB_V4WB 551 bool 552 help 553 ARM Architecture Version 4 TLB with writeback cache. 554 555config CPU_TLB_V4WBI 556 bool 557 help 558 ARM Architecture Version 4 TLB with writeback cache and invalidate 559 instruction cache entry. 560 561config CPU_TLB_FEROCEON 562 bool 563 help 564 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 565 566config CPU_TLB_FA 567 bool 568 help 569 Faraday ARM FA526 architecture, unified TLB with writeback cache 570 and invalidate instruction cache entry. Branch target buffer is 571 also supported. 572 573config CPU_TLB_V6 574 bool 575 576config CPU_TLB_V7 577 bool 578 579endif 580 581config CPU_HAS_ASID 582 bool 583 help 584 This indicates whether the CPU has the ASID register; used to 585 tag TLB and possibly cache entries. 586 587config CPU_CP15 588 bool 589 help 590 Processor has the CP15 register. 591 592config CPU_CP15_MMU 593 bool 594 select CPU_CP15 595 help 596 Processor has the CP15 register, which has MMU related registers. 597 598config CPU_CP15_MPU 599 bool 600 select CPU_CP15 601 help 602 Processor has the CP15 register, which has MPU related registers. 603 604# 605# CPU supports 36-bit I/O 606# 607config IO_36 608 bool 609 610comment "Processor Features" 611 612config ARM_THUMB 613 bool "Support Thumb user binaries" 614 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON 615 default y 616 help 617 Say Y if you want to include kernel support for running user space 618 Thumb binaries. 619 620 The Thumb instruction set is a compressed form of the standard ARM 621 instruction set resulting in smaller binaries at the expense of 622 slightly less efficient code. 623 624 If you don't know what this all is, saying Y is a safe choice. 625 626config ARM_THUMBEE 627 bool "Enable ThumbEE CPU extension" 628 depends on CPU_V7 629 help 630 Say Y here if you have a CPU with the ThumbEE extension and code to 631 make use of it. Say N for code that can run on CPUs without ThumbEE. 632 633config CPU_BIG_ENDIAN 634 bool "Build big-endian kernel" 635 depends on ARCH_SUPPORTS_BIG_ENDIAN 636 help 637 Say Y if you plan on running a kernel in big-endian mode. 638 Note that your board must be properly built and your board 639 port must properly enable any big-endian related features 640 of your chipset/board/processor. 641 642config CPU_ENDIAN_BE8 643 bool 644 depends on CPU_BIG_ENDIAN 645 default CPU_V6 || CPU_V7 646 help 647 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. 648 649config CPU_ENDIAN_BE32 650 bool 651 depends on CPU_BIG_ENDIAN 652 default !CPU_ENDIAN_BE8 653 help 654 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. 655 656config CPU_HIGH_VECTOR 657 depends on !MMU && CPU_CP15 && !CPU_ARM740T 658 bool "Select the High exception vector" 659 help 660 Say Y here to select high exception vector(0xFFFF0000~). 661 The exception vector can be vary depending on the platform 662 design in nommu mode. If your platform needs to select 663 high exception vector, say Y. 664 Otherwise or if you are unsure, say N, and the low exception 665 vector (0x00000000~) will be used. 666 667config CPU_ICACHE_DISABLE 668 bool "Disable I-Cache (I-bit)" 669 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 670 help 671 Say Y here to disable the processor instruction cache. Unless 672 you have a reason not to or are unsure, say N. 673 674config CPU_DCACHE_DISABLE 675 bool "Disable D-Cache (C-bit)" 676 depends on CPU_CP15 677 help 678 Say Y here to disable the processor data cache. Unless 679 you have a reason not to or are unsure, say N. 680 681config CPU_DCACHE_SIZE 682 hex 683 depends on CPU_ARM740T || CPU_ARM946E 684 default 0x00001000 if CPU_ARM740T 685 default 0x00002000 # default size for ARM946E-S 686 help 687 Some cores are synthesizable to have various sized cache. For 688 ARM946E-S case, it can vary from 0KB to 1MB. 689 To support such cache operations, it is efficient to know the size 690 before compile time. 691 If your SoC is configured to have a different size, define the value 692 here with proper conditions. 693 694config CPU_DCACHE_WRITETHROUGH 695 bool "Force write through D-cache" 696 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE 697 default y if CPU_ARM925T 698 help 699 Say Y here to use the data cache in writethrough mode. Unless you 700 specifically require this or are unsure, say N. 701 702config CPU_CACHE_ROUND_ROBIN 703 bool "Round robin I and D cache replacement algorithm" 704 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 705 help 706 Say Y here to use the predictable round-robin cache replacement 707 policy. Unless you specifically require this or are unsure, say N. 708 709config CPU_BPREDICT_DISABLE 710 bool "Disable branch prediction" 711 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 712 help 713 Say Y here to disable branch prediction. If unsure, say N. 714 715config TLS_REG_EMUL 716 bool 717 help 718 An SMP system using a pre-ARMv6 processor (there are apparently 719 a few prototypes like that in existence) and therefore access to 720 that required register must be emulated. 721 722config HAS_TLS_REG 723 bool 724 depends on !TLS_REG_EMUL 725 default y if SMP || CPU_32v7 726 help 727 This selects support for the CP15 thread register. 728 It is defined to be available on some ARMv6 processors (including 729 all SMP capable ARMv6's) or later processors. User space may 730 assume directly accessing that register and always obtain the 731 expected value only on ARMv7 and above. 732 733config NEEDS_SYSCALL_FOR_CMPXCHG 734 bool 735 help 736 SMP on a pre-ARMv6 processor? Well OK then. 737 Forget about fast user space cmpxchg support. 738 It is just not possible. 739 740config OUTER_CACHE 741 bool 742 743config CACHE_FEROCEON_L2 744 bool "Enable the Feroceon L2 cache controller" 745 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 746 default y 747 select OUTER_CACHE 748 help 749 This option enables the Feroceon L2 cache controller. 750 751config CACHE_FEROCEON_L2_WRITETHROUGH 752 bool "Force Feroceon L2 cache write through" 753 depends on CACHE_FEROCEON_L2 754 help 755 Say Y here to use the Feroceon L2 cache in writethrough mode. 756 Unless you specifically require this, say N for writeback mode. 757 758config CACHE_L2X0 759 bool "Enable the L2x0 outer cache controller" 760 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 761 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK 762 default y 763 select OUTER_CACHE 764 help 765 This option enables the L2x0 PrimeCell. 766 767config CACHE_XSC3L2 768 bool "Enable the L2 cache on XScale3" 769 depends on CPU_XSC3 770 default y 771 select OUTER_CACHE 772 help 773 This option enables the L2 cache on XScale3. 774 775config ARM_L1_CACHE_SHIFT 776 int 777 default 6 if ARCH_OMAP3 778 default 5 779