164b889b3SMichal Simek /* 264b889b3SMichal Simek * Xilinx SLCR driver 364b889b3SMichal Simek * 464b889b3SMichal Simek * Copyright (c) 2011-2013 Xilinx Inc. 564b889b3SMichal Simek * 664b889b3SMichal Simek * This program is free software; you can redistribute it and/or 764b889b3SMichal Simek * modify it under the terms of the GNU General Public License 864b889b3SMichal Simek * as published by the Free Software Foundation; either version 964b889b3SMichal Simek * 2 of the License, or (at your option) any later version. 1064b889b3SMichal Simek * 1164b889b3SMichal Simek * You should have received a copy of the GNU General Public 1264b889b3SMichal Simek * License along with this program; if not, write to the Free 1364b889b3SMichal Simek * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 1464b889b3SMichal Simek * 02139, USA. 1564b889b3SMichal Simek */ 1664b889b3SMichal Simek 1764b889b3SMichal Simek #include <linux/io.h> 1864b889b3SMichal Simek #include <linux/of_address.h> 1964b889b3SMichal Simek #include <linux/clk/zynq.h> 2064b889b3SMichal Simek #include "common.h" 2164b889b3SMichal Simek 22b5f177ffSSoren Brinkmann /* register offsets */ 23b5f177ffSSoren Brinkmann #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ 2496790f0aSMichal Simek #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ 25b5f177ffSSoren Brinkmann #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ 26b5f177ffSSoren Brinkmann #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ 27aa7eb2bbSMichal Simek 28b5f177ffSSoren Brinkmann #define SLCR_UNLOCK_MAGIC 0xDF0D 29aa7eb2bbSMichal Simek #define SLCR_A9_CPU_CLKSTOP 0x10 30aa7eb2bbSMichal Simek #define SLCR_A9_CPU_RST 0x1 31aa7eb2bbSMichal Simek 3264b889b3SMichal Simek void __iomem *zynq_slcr_base; 3364b889b3SMichal Simek 3464b889b3SMichal Simek /** 3596790f0aSMichal Simek * zynq_slcr_system_reset - Reset the entire system. 3696790f0aSMichal Simek */ 3796790f0aSMichal Simek void zynq_slcr_system_reset(void) 3896790f0aSMichal Simek { 3996790f0aSMichal Simek u32 reboot; 4096790f0aSMichal Simek 4196790f0aSMichal Simek /* 4296790f0aSMichal Simek * Unlock the SLCR then reset the system. 4396790f0aSMichal Simek * Note that this seems to require raw i/o 4496790f0aSMichal Simek * functions or there's a lockup? 4596790f0aSMichal Simek */ 46b5f177ffSSoren Brinkmann writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); 4796790f0aSMichal Simek 4896790f0aSMichal Simek /* 4996790f0aSMichal Simek * Clear 0x0F000000 bits of reboot status register to workaround 5096790f0aSMichal Simek * the FSBL not loading the bitstream after soft-reboot 5196790f0aSMichal Simek * This is a temporary solution until we know more. 5296790f0aSMichal Simek */ 53b5f177ffSSoren Brinkmann reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); 54b5f177ffSSoren Brinkmann writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); 5596790f0aSMichal Simek writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); 5696790f0aSMichal Simek } 5796790f0aSMichal Simek 5896790f0aSMichal Simek /** 59aa7eb2bbSMichal Simek * zynq_slcr_cpu_start - Start cpu 60aa7eb2bbSMichal Simek * @cpu: cpu number 61aa7eb2bbSMichal Simek */ 62aa7eb2bbSMichal Simek void zynq_slcr_cpu_start(int cpu) 63aa7eb2bbSMichal Simek { 64*3db9e860SSoren Brinkmann u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); 65*3db9e860SSoren Brinkmann reg &= ~(SLCR_A9_CPU_RST << cpu); 66*3db9e860SSoren Brinkmann writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); 67*3db9e860SSoren Brinkmann reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); 68*3db9e860SSoren Brinkmann writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); 69aa7eb2bbSMichal Simek } 70aa7eb2bbSMichal Simek 71aa7eb2bbSMichal Simek /** 72aa7eb2bbSMichal Simek * zynq_slcr_cpu_stop - Stop cpu 73aa7eb2bbSMichal Simek * @cpu: cpu number 74aa7eb2bbSMichal Simek */ 75aa7eb2bbSMichal Simek void zynq_slcr_cpu_stop(int cpu) 76aa7eb2bbSMichal Simek { 77*3db9e860SSoren Brinkmann u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); 78*3db9e860SSoren Brinkmann reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; 79*3db9e860SSoren Brinkmann writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); 80aa7eb2bbSMichal Simek } 81aa7eb2bbSMichal Simek 82aa7eb2bbSMichal Simek /** 8364b889b3SMichal Simek * zynq_slcr_init 8464b889b3SMichal Simek * Returns 0 on success, negative errno otherwise. 8564b889b3SMichal Simek * 8664b889b3SMichal Simek * Called early during boot from platform code to remap SLCR area. 8764b889b3SMichal Simek */ 8864b889b3SMichal Simek int __init zynq_slcr_init(void) 8964b889b3SMichal Simek { 9064b889b3SMichal Simek struct device_node *np; 9164b889b3SMichal Simek 9264b889b3SMichal Simek np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); 9364b889b3SMichal Simek if (!np) { 9464b889b3SMichal Simek pr_err("%s: no slcr node found\n", __func__); 9564b889b3SMichal Simek BUG(); 9664b889b3SMichal Simek } 9764b889b3SMichal Simek 9864b889b3SMichal Simek zynq_slcr_base = of_iomap(np, 0); 9964b889b3SMichal Simek if (!zynq_slcr_base) { 10064b889b3SMichal Simek pr_err("%s: Unable to map I/O memory\n", __func__); 10164b889b3SMichal Simek BUG(); 10264b889b3SMichal Simek } 10364b889b3SMichal Simek 10464b889b3SMichal Simek /* unlock the SLCR so that registers can be changed */ 105b5f177ffSSoren Brinkmann writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); 10664b889b3SMichal Simek 10764b889b3SMichal Simek pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); 10864b889b3SMichal Simek 10930e1e285SSoren Brinkmann zynq_clock_init(zynq_slcr_base); 11064b889b3SMichal Simek 11164b889b3SMichal Simek of_node_put(np); 11264b889b3SMichal Simek 11364b889b3SMichal Simek return 0; 11464b889b3SMichal Simek } 115