xref: /linux/arch/arm/mach-zynq/slcr.c (revision 3329659df0300d1d0aa22f5e7063f83a88ef92aa)
164b889b3SMichal Simek /*
264b889b3SMichal Simek  * Xilinx SLCR driver
364b889b3SMichal Simek  *
464b889b3SMichal Simek  * Copyright (c) 2011-2013 Xilinx Inc.
564b889b3SMichal Simek  *
664b889b3SMichal Simek  * This program is free software; you can redistribute it and/or
764b889b3SMichal Simek  * modify it under the terms of the GNU General Public License
864b889b3SMichal Simek  * as published by the Free Software Foundation; either version
964b889b3SMichal Simek  * 2 of the License, or (at your option) any later version.
1064b889b3SMichal Simek  *
1164b889b3SMichal Simek  * You should have received a copy of the GNU General Public
1264b889b3SMichal Simek  * License along with this program; if not, write to the Free
1364b889b3SMichal Simek  * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
1464b889b3SMichal Simek  * 02139, USA.
1564b889b3SMichal Simek  */
1664b889b3SMichal Simek 
1764b889b3SMichal Simek #include <linux/io.h>
18016f4dcaSMichal Simek #include <linux/mfd/syscon.h>
1964b889b3SMichal Simek #include <linux/of_address.h>
20016f4dcaSMichal Simek #include <linux/regmap.h>
2164b889b3SMichal Simek #include <linux/clk/zynq.h>
2264b889b3SMichal Simek #include "common.h"
2364b889b3SMichal Simek 
24b5f177ffSSoren Brinkmann /* register offsets */
25b5f177ffSSoren Brinkmann #define SLCR_UNLOCK_OFFSET		0x8   /* SCLR unlock register */
2696790f0aSMichal Simek #define SLCR_PS_RST_CTRL_OFFSET		0x200 /* PS Software Reset Control */
27b5f177ffSSoren Brinkmann #define SLCR_A9_CPU_RST_CTRL_OFFSET	0x244 /* CPU Software Reset Control */
28b5f177ffSSoren Brinkmann #define SLCR_REBOOT_STATUS_OFFSET	0x258 /* PS Reboot Status */
2900f7dc63SMichal Simek #define SLCR_PSS_IDCODE			0x530 /* PS IDCODE */
30aa7eb2bbSMichal Simek 
31b5f177ffSSoren Brinkmann #define SLCR_UNLOCK_MAGIC		0xDF0D
32aa7eb2bbSMichal Simek #define SLCR_A9_CPU_CLKSTOP		0x10
33aa7eb2bbSMichal Simek #define SLCR_A9_CPU_RST			0x1
3400f7dc63SMichal Simek #define SLCR_PSS_IDCODE_DEVICE_SHIFT	12
3500f7dc63SMichal Simek #define SLCR_PSS_IDCODE_DEVICE_MASK	0x1F
36aa7eb2bbSMichal Simek 
377b274efeSSteffen Trumtrar static void __iomem *zynq_slcr_base;
38016f4dcaSMichal Simek static struct regmap *zynq_slcr_regmap;
3964b889b3SMichal Simek 
4064b889b3SMichal Simek /**
41871c6971SMichal Simek  * zynq_slcr_write - Write to a register in SLCR block
42871c6971SMichal Simek  *
43871c6971SMichal Simek  * @val:	Value to write to the register
44871c6971SMichal Simek  * @offset:	Register offset in SLCR block
45871c6971SMichal Simek  *
46871c6971SMichal Simek  * Return:	a negative value on error, 0 on success
47871c6971SMichal Simek  */
48871c6971SMichal Simek static int zynq_slcr_write(u32 val, u32 offset)
49871c6971SMichal Simek {
50871c6971SMichal Simek 	return regmap_write(zynq_slcr_regmap, offset, val);
51871c6971SMichal Simek }
52871c6971SMichal Simek 
53871c6971SMichal Simek /**
54871c6971SMichal Simek  * zynq_slcr_read - Read a register in SLCR block
55871c6971SMichal Simek  *
56871c6971SMichal Simek  * @val:	Pointer to value to be read from SLCR
57871c6971SMichal Simek  * @offset:	Register offset in SLCR block
58871c6971SMichal Simek  *
59871c6971SMichal Simek  * Return:	a negative value on error, 0 on success
60871c6971SMichal Simek  */
61871c6971SMichal Simek static int zynq_slcr_read(u32 *val, u32 offset)
62871c6971SMichal Simek {
63871c6971SMichal Simek 	return regmap_read(zynq_slcr_regmap, offset, val);
64871c6971SMichal Simek }
65871c6971SMichal Simek 
66871c6971SMichal Simek /**
6756880073SMichal Simek  * zynq_slcr_unlock - Unlock SLCR registers
6856880073SMichal Simek  *
6956880073SMichal Simek  * Return:	a negative value on error, 0 on success
7056880073SMichal Simek  */
7156880073SMichal Simek static inline int zynq_slcr_unlock(void)
7256880073SMichal Simek {
7356880073SMichal Simek 	zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
7456880073SMichal Simek 
7556880073SMichal Simek 	return 0;
7656880073SMichal Simek }
7756880073SMichal Simek 
7856880073SMichal Simek /**
7900f7dc63SMichal Simek  * zynq_slcr_get_device_id - Read device code id
8000f7dc63SMichal Simek  *
8100f7dc63SMichal Simek  * Return:	Device code id
8200f7dc63SMichal Simek  */
8300f7dc63SMichal Simek u32 zynq_slcr_get_device_id(void)
8400f7dc63SMichal Simek {
8500f7dc63SMichal Simek 	u32 val;
8600f7dc63SMichal Simek 
8700f7dc63SMichal Simek 	zynq_slcr_read(&val, SLCR_PSS_IDCODE);
8800f7dc63SMichal Simek 	val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
8900f7dc63SMichal Simek 	val &= SLCR_PSS_IDCODE_DEVICE_MASK;
9000f7dc63SMichal Simek 
9100f7dc63SMichal Simek 	return val;
9200f7dc63SMichal Simek }
9300f7dc63SMichal Simek 
9400f7dc63SMichal Simek /**
9596790f0aSMichal Simek  * zynq_slcr_system_reset - Reset the entire system.
9696790f0aSMichal Simek  */
9796790f0aSMichal Simek void zynq_slcr_system_reset(void)
9896790f0aSMichal Simek {
9996790f0aSMichal Simek 	u32 reboot;
10096790f0aSMichal Simek 
10196790f0aSMichal Simek 	/*
10296790f0aSMichal Simek 	 * Unlock the SLCR then reset the system.
10396790f0aSMichal Simek 	 * Note that this seems to require raw i/o
10496790f0aSMichal Simek 	 * functions or there's a lockup?
10596790f0aSMichal Simek 	 */
10656880073SMichal Simek 	zynq_slcr_unlock();
10796790f0aSMichal Simek 
10896790f0aSMichal Simek 	/*
10996790f0aSMichal Simek 	 * Clear 0x0F000000 bits of reboot status register to workaround
11096790f0aSMichal Simek 	 * the FSBL not loading the bitstream after soft-reboot
11196790f0aSMichal Simek 	 * This is a temporary solution until we know more.
11296790f0aSMichal Simek 	 */
113871c6971SMichal Simek 	zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
114871c6971SMichal Simek 	zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
115871c6971SMichal Simek 	zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
11696790f0aSMichal Simek }
11796790f0aSMichal Simek 
11896790f0aSMichal Simek /**
119aa7eb2bbSMichal Simek  * zynq_slcr_cpu_start - Start cpu
120aa7eb2bbSMichal Simek  * @cpu:	cpu number
121aa7eb2bbSMichal Simek  */
122aa7eb2bbSMichal Simek void zynq_slcr_cpu_start(int cpu)
123aa7eb2bbSMichal Simek {
124871c6971SMichal Simek 	u32 reg;
125871c6971SMichal Simek 
126871c6971SMichal Simek 	zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
1273db9e860SSoren Brinkmann 	reg &= ~(SLCR_A9_CPU_RST << cpu);
128871c6971SMichal Simek 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
1293db9e860SSoren Brinkmann 	reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
130871c6971SMichal Simek 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
13150c7960aSSoren Brinkmann 
13250c7960aSSoren Brinkmann 	zynq_slcr_cpu_state_write(cpu, false);
133aa7eb2bbSMichal Simek }
134aa7eb2bbSMichal Simek 
135aa7eb2bbSMichal Simek /**
136aa7eb2bbSMichal Simek  * zynq_slcr_cpu_stop - Stop cpu
137aa7eb2bbSMichal Simek  * @cpu:	cpu number
138aa7eb2bbSMichal Simek  */
139aa7eb2bbSMichal Simek void zynq_slcr_cpu_stop(int cpu)
140aa7eb2bbSMichal Simek {
141871c6971SMichal Simek 	u32 reg;
142871c6971SMichal Simek 
143871c6971SMichal Simek 	zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
1443db9e860SSoren Brinkmann 	reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
145871c6971SMichal Simek 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
146aa7eb2bbSMichal Simek }
147aa7eb2bbSMichal Simek 
148aa7eb2bbSMichal Simek /**
14950c7960aSSoren Brinkmann  * zynq_slcr_cpu_state - Read/write cpu state
15050c7960aSSoren Brinkmann  * @cpu:	cpu number
151016f4dcaSMichal Simek  *
15250c7960aSSoren Brinkmann  * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
15350c7960aSSoren Brinkmann  * 0 means cpu is running, 1 cpu is going to die.
15450c7960aSSoren Brinkmann  *
15550c7960aSSoren Brinkmann  * Return: true if cpu is running, false if cpu is going to die
15650c7960aSSoren Brinkmann  */
15750c7960aSSoren Brinkmann bool zynq_slcr_cpu_state_read(int cpu)
15850c7960aSSoren Brinkmann {
15950c7960aSSoren Brinkmann 	u32 state;
16050c7960aSSoren Brinkmann 
16150c7960aSSoren Brinkmann 	state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
16250c7960aSSoren Brinkmann 	state &= 1 << (31 - cpu);
16350c7960aSSoren Brinkmann 
16450c7960aSSoren Brinkmann 	return !state;
16550c7960aSSoren Brinkmann }
16650c7960aSSoren Brinkmann 
16750c7960aSSoren Brinkmann /**
16850c7960aSSoren Brinkmann  * zynq_slcr_cpu_state - Read/write cpu state
16950c7960aSSoren Brinkmann  * @cpu:	cpu number
17050c7960aSSoren Brinkmann  * @die:	cpu state - true if cpu is going to die
17150c7960aSSoren Brinkmann  *
17250c7960aSSoren Brinkmann  * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
17350c7960aSSoren Brinkmann  * 0 means cpu is running, 1 cpu is going to die.
17450c7960aSSoren Brinkmann  */
17550c7960aSSoren Brinkmann void zynq_slcr_cpu_state_write(int cpu, bool die)
17650c7960aSSoren Brinkmann {
17750c7960aSSoren Brinkmann 	u32 state, mask;
17850c7960aSSoren Brinkmann 
17950c7960aSSoren Brinkmann 	state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
18050c7960aSSoren Brinkmann 	mask = 1 << (31 - cpu);
18150c7960aSSoren Brinkmann 	if (die)
18250c7960aSSoren Brinkmann 		state |= mask;
18350c7960aSSoren Brinkmann 	else
18450c7960aSSoren Brinkmann 		state &= ~mask;
18550c7960aSSoren Brinkmann 	writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
18650c7960aSSoren Brinkmann }
18750c7960aSSoren Brinkmann 
18850c7960aSSoren Brinkmann /**
189016f4dcaSMichal Simek  * zynq_early_slcr_init - Early slcr init function
190016f4dcaSMichal Simek  *
191016f4dcaSMichal Simek  * Return:	0 on success, negative errno otherwise.
192016f4dcaSMichal Simek  *
193016f4dcaSMichal Simek  * Called very early during boot from platform code to unlock SLCR.
194016f4dcaSMichal Simek  */
195016f4dcaSMichal Simek int __init zynq_early_slcr_init(void)
196016f4dcaSMichal Simek {
19764b889b3SMichal Simek 	struct device_node *np;
19864b889b3SMichal Simek 
19964b889b3SMichal Simek 	np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
20064b889b3SMichal Simek 	if (!np) {
20164b889b3SMichal Simek 		pr_err("%s: no slcr node found\n", __func__);
20264b889b3SMichal Simek 		BUG();
20364b889b3SMichal Simek 	}
20464b889b3SMichal Simek 
20564b889b3SMichal Simek 	zynq_slcr_base = of_iomap(np, 0);
20664b889b3SMichal Simek 	if (!zynq_slcr_base) {
20764b889b3SMichal Simek 		pr_err("%s: Unable to map I/O memory\n", __func__);
20864b889b3SMichal Simek 		BUG();
20964b889b3SMichal Simek 	}
21064b889b3SMichal Simek 
2115e218280SSteffen Trumtrar 	np->data = (__force void *)zynq_slcr_base;
2125e218280SSteffen Trumtrar 
213*3329659dSMichal Simek 	zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
214*3329659dSMichal Simek 	if (IS_ERR(zynq_slcr_regmap)) {
215*3329659dSMichal Simek 		pr_err("%s: failed to find zynq-slcr\n", __func__);
216*3329659dSMichal Simek 		return -ENODEV;
217*3329659dSMichal Simek 	}
218*3329659dSMichal Simek 
21964b889b3SMichal Simek 	/* unlock the SLCR so that registers can be changed */
22056880073SMichal Simek 	zynq_slcr_unlock();
22164b889b3SMichal Simek 
22264b889b3SMichal Simek 	pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
22364b889b3SMichal Simek 
22464b889b3SMichal Simek 	of_node_put(np);
22564b889b3SMichal Simek 
22664b889b3SMichal Simek 	return 0;
22764b889b3SMichal Simek }
228