1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * This file contains common function prototypes to avoid externs 4 * in the c files. 5 * 6 * Copyright (C) 2011 Xilinx 7 */ 8 9 #ifndef __MACH_ZYNQ_COMMON_H__ 10 #define __MACH_ZYNQ_COMMON_H__ 11 12 extern int zynq_early_slcr_init(void); 13 extern void zynq_slcr_cpu_stop(int cpu); 14 extern void zynq_slcr_cpu_start(int cpu); 15 extern bool zynq_slcr_cpu_state_read(int cpu); 16 extern void zynq_slcr_cpu_state_write(int cpu, bool die); 17 extern u32 zynq_slcr_get_device_id(void); 18 19 #ifdef CONFIG_SMP 20 extern char zynq_secondary_trampoline; 21 extern char zynq_secondary_trampoline_jump; 22 extern char zynq_secondary_trampoline_end; 23 extern int zynq_cpun_start(u32 address, int cpu); 24 extern const struct smp_operations zynq_smp_ops; 25 #endif 26 27 extern void __iomem *zynq_scu_base; 28 29 void zynq_pm_late_init(void); 30 31 static inline void zynq_core_pm_init(void) 32 { 33 /* A9 clock gating */ 34 asm volatile ("mrc p15, 0, r12, c15, c0, 0\n" 35 "orr r12, r12, #1\n" 36 "mcr p15, 0, r12, c15, c0, 0\n" 37 : /* no outputs */ 38 : /* no inputs */ 39 : "r12"); 40 } 41 42 #endif 43