1 /* 2 * NVIDIA Tegra SoC device tree board support 3 * 4 * Copyright (C) 2011, 2013, NVIDIA Corporation 5 * Copyright (C) 2010 Secret Lab Technologies, Ltd. 6 * Copyright (C) 2010 Google, Inc. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clk/tegra.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/irqchip.h> 25 #include <linux/irqdomain.h> 26 #include <linux/kernel.h> 27 #include <linux/of_address.h> 28 #include <linux/of_fdt.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 #include <linux/pda_power.h> 32 #include <linux/platform_device.h> 33 #include <linux/serial_8250.h> 34 #include <linux/slab.h> 35 #include <linux/sys_soc.h> 36 #include <linux/usb/tegra_usb_phy.h> 37 38 #include <soc/tegra/fuse.h> 39 #include <soc/tegra/pmc.h> 40 41 #include <asm/hardware/cache-l2x0.h> 42 #include <asm/mach/arch.h> 43 #include <asm/mach/time.h> 44 #include <asm/mach-types.h> 45 #include <asm/setup.h> 46 #include <asm/trusted_foundations.h> 47 48 #include "board.h" 49 #include "common.h" 50 #include "cpuidle.h" 51 #include "iomap.h" 52 #include "irq.h" 53 #include "pm.h" 54 #include "reset.h" 55 #include "sleep.h" 56 57 /* 58 * Storage for debug-macro.S's state. 59 * 60 * This must be in .data not .bss so that it gets initialized each time the 61 * kernel is loaded. The data is declared here rather than debug-macro.S so 62 * that multiple inclusions of debug-macro.S point at the same data. 63 */ 64 u32 tegra_uart_config[3] = { 65 /* Debug UART initialization required */ 66 1, 67 /* Debug UART physical address */ 68 0, 69 /* Debug UART virtual address */ 70 0, 71 }; 72 73 static void __init tegra_init_early(void) 74 { 75 of_register_trusted_foundations(); 76 tegra_cpu_reset_handler_init(); 77 } 78 79 static void __init tegra_dt_init_irq(void) 80 { 81 tegra_init_irq(); 82 irqchip_init(); 83 tegra_legacy_irq_syscore_init(); 84 } 85 86 static void __init tegra_dt_init(void) 87 { 88 struct soc_device_attribute *soc_dev_attr; 89 struct soc_device *soc_dev; 90 struct device *parent = NULL; 91 92 tegra_clocks_apply_init_table(); 93 94 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 95 if (!soc_dev_attr) 96 goto out; 97 98 soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra"); 99 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", 100 tegra_sku_info.revision); 101 soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 102 103 soc_dev = soc_device_register(soc_dev_attr); 104 if (IS_ERR(soc_dev)) { 105 kfree(soc_dev_attr->family); 106 kfree(soc_dev_attr->revision); 107 kfree(soc_dev_attr->soc_id); 108 kfree(soc_dev_attr); 109 goto out; 110 } 111 112 parent = soc_device_to_device(soc_dev); 113 114 /* 115 * Finished with the static registrations now; fill in the missing 116 * devices 117 */ 118 out: 119 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); 120 } 121 122 static void __init paz00_init(void) 123 { 124 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 125 tegra_paz00_wifikill_init(); 126 } 127 128 static struct { 129 char *machine; 130 void (*init)(void); 131 } board_init_funcs[] = { 132 { "compal,paz00", paz00_init }, 133 }; 134 135 static void __init tegra_dt_init_late(void) 136 { 137 int i; 138 139 tegra_init_suspend(); 140 tegra_cpuidle_init(); 141 142 for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { 143 if (of_machine_is_compatible(board_init_funcs[i].machine)) { 144 board_init_funcs[i].init(); 145 break; 146 } 147 } 148 } 149 150 static const char * const tegra_dt_board_compat[] = { 151 "nvidia,tegra124", 152 "nvidia,tegra114", 153 "nvidia,tegra30", 154 "nvidia,tegra20", 155 NULL 156 }; 157 158 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") 159 .l2c_aux_val = 0x3c400001, 160 .l2c_aux_mask = 0xc20fc3fe, 161 .smp = smp_ops(tegra_smp_ops), 162 .map_io = tegra_map_common_io, 163 .init_early = tegra_init_early, 164 .init_irq = tegra_dt_init_irq, 165 .init_machine = tegra_dt_init, 166 .init_late = tegra_dt_init_late, 167 .restart = tegra_pmc_restart, 168 .dt_compat = tegra_dt_board_compat, 169 MACHINE_END 170