1 /* 2 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __MACH_TEGRA_SLEEP_H 18 #define __MACH_TEGRA_SLEEP_H 19 20 #include "iomap.h" 21 22 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ 23 + IO_CPU_VIRT) 24 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ 25 + IO_PPSB_VIRT) 26 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \ 27 + IO_PPSB_VIRT) 28 29 #ifdef __ASSEMBLY__ 30 /* returns the offset of the flow controller halt register for a cpu */ 31 .macro cpu_to_halt_reg rd, rcpu 32 cmp \rcpu, #0 33 subne \rd, \rcpu, #1 34 movne \rd, \rd, lsl #3 35 addne \rd, \rd, #0x14 36 moveq \rd, #0 37 .endm 38 39 /* returns the offset of the flow controller csr register for a cpu */ 40 .macro cpu_to_csr_reg rd, rcpu 41 cmp \rcpu, #0 42 subne \rd, \rcpu, #1 43 movne \rd, \rd, lsl #3 44 addne \rd, \rd, #0x18 45 moveq \rd, #8 46 .endm 47 48 /* returns the ID of the current processor */ 49 .macro cpu_id, rd 50 mrc p15, 0, \rd, c0, c0, 5 51 and \rd, \rd, #0xF 52 .endm 53 54 /* loads a 32-bit value into a register without a data access */ 55 .macro mov32, reg, val 56 movw \reg, #:lower16:\val 57 movt \reg, #:upper16:\val 58 .endm 59 60 /* Macro to exit SMP coherency. */ 61 .macro exit_smp, tmp1, tmp2 62 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR 63 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW 64 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR 65 isb 66 cpu_id \tmp1 67 mov \tmp1, \tmp1, lsl #2 68 mov \tmp2, #0xf 69 mov \tmp2, \tmp2, lsl \tmp1 70 mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC 71 str \tmp2, [\tmp1] @ invalidate SCU tags for CPU 72 dsb 73 .endm 74 75 /* Macro to resume & re-enable L2 cache */ 76 #ifndef L2X0_CTRL_EN 77 #define L2X0_CTRL_EN 1 78 #endif 79 80 #ifdef CONFIG_CACHE_L2X0 81 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs 82 adr \tmp1, \phys_l2x0_saved_regs 83 ldr \tmp1, [\tmp1] 84 ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] 85 ldr \tmp3, [\tmp2, #L2X0_CTRL] 86 tst \tmp3, #L2X0_CTRL_EN 87 bne exit_l2_resume 88 ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY] 89 str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL] 90 ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY] 91 str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL] 92 ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL] 93 str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL] 94 ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL] 95 str \tmp3, [\tmp2, #L2X0_POWER_CTRL] 96 ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL] 97 str \tmp3, [\tmp2, #L2X0_AUX_CTRL] 98 mov \tmp3, #L2X0_CTRL_EN 99 str \tmp3, [\tmp2, #L2X0_CTRL] 100 exit_l2_resume: 101 .endm 102 #else /* CONFIG_CACHE_L2X0 */ 103 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs 104 .endm 105 #endif /* CONFIG_CACHE_L2X0 */ 106 #else 107 void tegra_resume(void); 108 int tegra_sleep_cpu_finish(unsigned long); 109 110 #ifdef CONFIG_HOTPLUG_CPU 111 void tegra20_hotplug_init(void); 112 void tegra30_hotplug_init(void); 113 #else 114 static inline void tegra20_hotplug_init(void) {} 115 static inline void tegra30_hotplug_init(void) {} 116 #endif 117 118 int tegra30_sleep_cpu_secondary_finish(unsigned long); 119 void tegra30_tear_down_cpu(void); 120 121 #endif 122 #endif 123