1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. 4 */ 5 6#include <linux/linkage.h> 7 8#include <soc/tegra/flowctrl.h> 9#include <soc/tegra/fuse.h> 10 11#include <asm/asm-offsets.h> 12#include <asm/assembler.h> 13#include <asm/cache.h> 14 15#include "irammap.h" 16#include "sleep.h" 17 18#define EMC_CFG 0xc 19#define EMC_ADR_CFG 0x10 20#define EMC_TIMING_CONTROL 0x28 21#define EMC_NOP 0xdc 22#define EMC_SELF_REF 0xe0 23#define EMC_MRW 0xe8 24#define EMC_FBIO_CFG5 0x104 25#define EMC_AUTO_CAL_CONFIG 0x2a4 26#define EMC_AUTO_CAL_INTERVAL 0x2a8 27#define EMC_AUTO_CAL_STATUS 0x2ac 28#define EMC_REQ_CTRL 0x2b0 29#define EMC_CFG_DIG_DLL 0x2bc 30#define EMC_EMC_STATUS 0x2b4 31#define EMC_ZCAL_INTERVAL 0x2e0 32#define EMC_ZQ_CAL 0x2ec 33#define EMC_XM2VTTGENPADCTRL 0x310 34#define EMC_XM2VTTGENPADCTRL2 0x314 35 36#define PMC_CTRL 0x0 37#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */ 38 39#define PMC_PLLP_WB0_OVERRIDE 0xf8 40#define PMC_IO_DPD_REQ 0x1b8 41#define PMC_IO_DPD_STATUS 0x1bc 42 43#define CLK_RESET_CCLK_BURST 0x20 44#define CLK_RESET_CCLK_DIVIDER 0x24 45#define CLK_RESET_SCLK_BURST 0x28 46#define CLK_RESET_SCLK_DIVIDER 0x2c 47 48#define CLK_RESET_PLLC_BASE 0x80 49#define CLK_RESET_PLLC_MISC 0x8c 50#define CLK_RESET_PLLM_BASE 0x90 51#define CLK_RESET_PLLM_MISC 0x9c 52#define CLK_RESET_PLLP_BASE 0xa0 53#define CLK_RESET_PLLP_MISC 0xac 54#define CLK_RESET_PLLA_BASE 0xb0 55#define CLK_RESET_PLLA_MISC 0xbc 56#define CLK_RESET_PLLX_BASE 0xe0 57#define CLK_RESET_PLLX_MISC 0xe4 58#define CLK_RESET_PLLX_MISC3 0x518 59#define CLK_RESET_PLLX_MISC3_IDDQ 3 60#define CLK_RESET_PLLM_MISC_IDDQ 5 61#define CLK_RESET_PLLC_MISC_IDDQ 26 62#define CLK_RESET_PLLP_RESHIFT 0x528 63#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b 64#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3 65 66#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 67 68#define MSELECT_CLKM (0x3 << 30) 69 70#define LOCK_DELAY 50 /* safety delay after lock is detected */ 71 72#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ 73 74#define PLLA_STORE_MASK (1 << 0) 75#define PLLC_STORE_MASK (1 << 1) 76#define PLLM_STORE_MASK (1 << 2) 77#define PLLP_STORE_MASK (1 << 3) 78#define PLLX_STORE_MASK (1 << 4) 79#define PLLM_PMC_STORE_MASK (1 << 5) 80 81.arch armv7-a 82 83.macro emc_device_mask, rd, base 84 ldr \rd, [\base, #EMC_ADR_CFG] 85 tst \rd, #0x1 86 moveq \rd, #(0x1 << 8) @ just 1 device 87 movne \rd, #(0x3 << 8) @ 2 devices 88.endm 89 90.macro emc_timing_update, rd, base 91 mov \rd, #1 92 str \rd, [\base, #EMC_TIMING_CONTROL] 931001: 94 ldr \rd, [\base, #EMC_EMC_STATUS] 95 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear 96 bne 1001b 97.endm 98 99.macro test_pll_state, rd, test_mask 100 ldr \rd, tegra_pll_state 101 tst \rd, #\test_mask 102.endm 103 104.macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask 105 ldr \rd, [\r_car_base, #\pll_base] 106 tst \rd, #(1 << 30) 107 ldr \rd, tegra_pll_state 108 biceq \rd, \rd, #\pll_mask 109 orrne \rd, \rd, #\pll_mask 110 adr \tmp, tegra_pll_state 111 str \rd, [\tmp] 112.endm 113 114.macro store_pllm_pmc_state, rd, tmp, pmc_base 115 ldr \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] 116 tst \rd, #(1 << 12) 117 ldr \rd, tegra_pll_state 118 biceq \rd, \rd, #PLLM_PMC_STORE_MASK 119 orrne \rd, \rd, #PLLM_PMC_STORE_MASK 120 adr \tmp, tegra_pll_state 121 str \rd, [\tmp] 122.endm 123 124.macro pllm_pmc_enable, rd, pmc_base 125 test_pll_state \rd, PLLM_PMC_STORE_MASK 126 127 ldrne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] 128 orrne \rd, \rd, #(1 << 12) 129 strne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] 130.endm 131 132.macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask 133 test_pll_state \rd, \test_mask 134 beq 1f 135 136 ldr \rd, [\r_car_base, #\pll_base] 137 tst \rd, #(1 << 30) 138 orreq \rd, \rd, #(1 << 30) 139 streq \rd, [\r_car_base, #\pll_base] 140 /* Enable lock detector */ 141 .if \pll_misc 142 ldr \rd, [\r_car_base, #\pll_misc] 143 bic \rd, \rd, #(1 << 18) 144 str \rd, [\r_car_base, #\pll_misc] 145 ldr \rd, [\r_car_base, #\pll_misc] 146 ldr \rd, [\r_car_base, #\pll_misc] 147 orr \rd, \rd, #(1 << 18) 148 str \rd, [\r_car_base, #\pll_misc] 149 .endif 1501: 151.endm 152 153.macro pll_locked, rd, r_car_base, pll_base, test_mask 154 test_pll_state \rd, \test_mask 155 beq 2f 1561: 157 ldr \rd, [\r_car_base, #\pll_base] 158 tst \rd, #(1 << 27) 159 beq 1b 1602: 161.endm 162 163.macro pll_iddq_exit, rd, car, iddq, iddq_bit 164 ldr \rd, [\car, #\iddq] 165 bic \rd, \rd, #(1<<\iddq_bit) 166 str \rd, [\car, #\iddq] 167.endm 168 169.macro pll_iddq_entry, rd, car, iddq, iddq_bit 170 ldr \rd, [\car, #\iddq] 171 orr \rd, \rd, #(1<<\iddq_bit) 172 str \rd, [\car, #\iddq] 173.endm 174 175#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 176/* 177 * tegra30_hotplug_shutdown(void) 178 * 179 * Powergates the current CPU. 180 * Should never return. 181 */ 182ENTRY(tegra30_hotplug_shutdown) 183 /* Powergate this CPU */ 184 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN 185 bl tegra30_cpu_shutdown 186 ret lr @ should never get here 187ENDPROC(tegra30_hotplug_shutdown) 188 189/* 190 * tegra30_cpu_shutdown(unsigned long flags) 191 * 192 * Puts the current CPU in wait-for-event mode on the flow controller 193 * and powergates it -- flags (in R0) indicate the request type. 194 * 195 * r10 = SoC ID 196 * corrupts r0-r4, r10-r12 197 */ 198ENTRY(tegra30_cpu_shutdown) 199 cpu_id r3 200 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10 201 cmp r10, #TEGRA30 202 bne _no_cpu0_chk @ It's not Tegra30 203 204 cmp r3, #0 205 reteq lr @ Must never be called for CPU 0 206_no_cpu0_chk: 207 208 ldr r12, =TEGRA_FLOW_CTRL_VIRT 209 cpu_to_csr_reg r1, r3 210 add r1, r1, r12 @ virtual CSR address for this CPU 211 cpu_to_halt_reg r2, r3 212 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU 213 214 /* 215 * Clear this CPU's "event" and "interrupt" flags and power gate 216 * it when halting but not before it is in the "WFE" state. 217 */ 218 movw r12, \ 219 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ 220 FLOW_CTRL_CSR_ENABLE 221 cmp r10, #TEGRA30 222 moveq r4, #(1 << 4) @ wfe bitmap 223 movne r4, #(1 << 8) @ wfi bitmap 224 ARM( orr r12, r12, r4, lsl r3 ) 225 THUMB( lsl r4, r4, r3 ) 226 THUMB( orr r12, r12, r4 ) 227 str r12, [r1] 228 229 /* Halt this CPU. */ 230 mov r3, #0x400 231delay_1: 232 subs r3, r3, #1 @ delay as a part of wfe war. 233 bge delay_1; 234 cpsid a @ disable imprecise aborts. 235 ldr r3, [r1] @ read CSR 236 str r3, [r1] @ clear CSR 237 238 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN 239 beq flow_ctrl_setting_for_lp2 240 241 /* flow controller set up for hotplug */ 242 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug 243 b flow_ctrl_done 244flow_ctrl_setting_for_lp2: 245 /* flow controller set up for LP2 */ 246 cmp r10, #TEGRA30 247 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 248 movne r3, #FLOW_CTRL_WAITEVENT 249 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ 250 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ 251flow_ctrl_done: 252 cmp r10, #TEGRA30 253 str r3, [r2] 254 ldr r0, [r2] 255 b wfe_war 256 257__cpu_reset_again: 258 dsb 259 .align 5 260 wfeeq @ CPU should be power gated here 261 wfine 262wfe_war: 263 b __cpu_reset_again 264 265 /* 266 * 38 nop's, which fills rest of wfe cache line and 267 * 4 more cachelines with nop 268 */ 269 .rept 38 270 nop 271 .endr 272 b . @ should never get here 273 274ENDPROC(tegra30_cpu_shutdown) 275#endif 276 277#ifdef CONFIG_PM_SLEEP 278/* 279 * tegra30_sleep_core_finish(unsigned long v2p) 280 * 281 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to 282 * tegra30_tear_down_core in IRAM 283 */ 284ENTRY(tegra30_sleep_core_finish) 285 mov r4, r0 286 /* Flush, disable the L1 data cache and exit SMP */ 287 mov r0, #TEGRA_FLUSH_CACHE_ALL 288 bl tegra_disable_clean_inv_dcache 289 mov r0, r4 290 291 /* 292 * Preload all the address literals that are needed for the 293 * CPU power-gating process, to avoid loading from SDRAM which 294 * are not supported once SDRAM is put into self-refresh. 295 * LP0 / LP1 use physical address, since the MMU needs to be 296 * disabled before putting SDRAM into self-refresh to avoid 297 * memory access due to page table walks. 298 */ 299 mov32 r4, TEGRA_PMC_BASE 300 mov32 r5, TEGRA_CLK_RESET_BASE 301 mov32 r6, TEGRA_FLOW_CTRL_BASE 302 mov32 r7, TEGRA_TMRUS_BASE 303 304 mov32 r3, tegra_shut_off_mmu 305 add r3, r3, r0 306 307 mov32 r0, tegra30_tear_down_core 308 mov32 r1, tegra30_iram_start 309 sub r0, r0, r1 310 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA 311 add r0, r0, r1 312 313 ret r3 314ENDPROC(tegra30_sleep_core_finish) 315 316/* 317 * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg) 318 * 319 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. 320 */ 321ENTRY(tegra30_pm_secondary_cpu_suspend) 322 mov r7, lr 323 324 /* Flush and disable the L1 data cache */ 325 mov r0, #TEGRA_FLUSH_CACHE_LOUIS 326 bl tegra_disable_clean_inv_dcache 327 328 /* Powergate this CPU. */ 329 mov r0, #0 @ power mode flags (!hotplug) 330 bl tegra30_cpu_shutdown 331 mov r0, #1 @ never return here 332 ret r7 333ENDPROC(tegra30_pm_secondary_cpu_suspend) 334 335/* 336 * tegra30_tear_down_cpu 337 * 338 * Switches the CPU to enter sleep. 339 */ 340ENTRY(tegra30_tear_down_cpu) 341 mov32 r6, TEGRA_FLOW_CTRL_BASE 342 343 b tegra30_enter_sleep 344ENDPROC(tegra30_tear_down_cpu) 345 346/* START OF ROUTINES COPIED TO IRAM */ 347 .align L1_CACHE_SHIFT 348 .globl tegra30_iram_start 349tegra30_iram_start: 350 351/* 352 * tegra30_lp1_reset 353 * 354 * reset vector for LP1 restore; copied into IRAM during suspend. 355 * Brings the system back up to a safe staring point (SDRAM out of 356 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX, 357 * system clock running on the same PLL that it suspended at), and 358 * jumps to tegra_resume to restore virtual addressing. 359 * The physical address of tegra_resume expected to be stored in 360 * PMC_SCRATCH41. 361 * 362 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA. 363 */ 364ENTRY(tegra30_lp1_reset) 365 /* 366 * The CPU and system bus are running at 32KHz and executing from 367 * IRAM when this code is executed; immediately switch to CLKM and 368 * enable PLLP, PLLM, PLLC, PLLA and PLLX. 369 */ 370 mov32 r0, TEGRA_CLK_RESET_BASE 371 372 mov r1, #(1 << 28) 373 str r1, [r0, #CLK_RESET_SCLK_BURST] 374 str r1, [r0, #CLK_RESET_CCLK_BURST] 375 mov r1, #0 376 str r1, [r0, #CLK_RESET_CCLK_DIVIDER] 377 str r1, [r0, #CLK_RESET_SCLK_DIVIDER] 378 379 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 380 cmp r10, #TEGRA30 381 beq _no_pll_iddq_exit 382 383 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ 384 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ 385 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ 386 387 mov32 r7, TEGRA_TMRUS_BASE 388 ldr r1, [r7] 389 add r1, r1, #2 390 wait_until r1, r7, r3 391 392 /* enable PLLM via PMC */ 393 mov32 r2, TEGRA_PMC_BASE 394 pllm_pmc_enable r1, r2 395 396 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK 397 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK 398 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK 399 400 b _pll_m_c_x_done 401 402_no_pll_iddq_exit: 403 /* enable PLLM via PMC */ 404 mov32 r2, TEGRA_PMC_BASE 405 pllm_pmc_enable r1, r2 406 407 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK 408 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK 409 410_pll_m_c_x_done: 411 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK 412 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK 413 414 pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK 415 pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK 416 pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK 417 pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK 418 419 /* 420 * CPUFreq driver could select other PLL for CPU. PLLX will be 421 * enabled by the Tegra30 CLK driver on an as-needed basis, see 422 * tegra30_cpu_clock_resume(). 423 */ 424 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 425 cmp r1, #TEGRA30 426 beq 1f 427 428 pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK 429 430 ldr r1, [r0, #CLK_RESET_PLLP_BASE] 431 bic r1, r1, #(1<<31) @ disable PllP bypass 432 str r1, [r0, #CLK_RESET_PLLP_BASE] 433 434 mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT 435 str r1, [r0, #CLK_RESET_PLLP_RESHIFT] 4361: 437 438 mov32 r7, TEGRA_TMRUS_BASE 439 ldr r1, [r7] 440 add r1, r1, #LOCK_DELAY 441 wait_until r1, r7, r3 442 443 adr r5, tegra_sdram_pad_save 444 445 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT 446 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] 447 448 ldr r4, [r5, #0x1C] @ restore SCLK_BURST 449 str r4, [r0, #CLK_RESET_SCLK_BURST] 450 451 movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP 452 movt r4, #:upper16:((1 << 28) | (0x4)) 453 str r4, [r0, #CLK_RESET_CCLK_BURST] 454 455 /* Restore pad power state to normal */ 456 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS 457 mvn r1, r1 458 bic r1, r1, #(1 << 31) 459 orr r1, r1, #(1 << 30) 460 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF 461 462 cmp r10, #TEGRA30 463 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base 464 movteq r0, #:upper16:TEGRA_EMC_BASE 465 cmp r10, #TEGRA114 466 movweq r0, #:lower16:TEGRA_EMC0_BASE 467 movteq r0, #:upper16:TEGRA_EMC0_BASE 468 cmp r10, #TEGRA124 469 movweq r0, #:lower16:TEGRA124_EMC_BASE 470 movteq r0, #:upper16:TEGRA124_EMC_BASE 471 472exit_self_refresh: 473 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL 474 str r1, [r0, #EMC_XM2VTTGENPADCTRL] 475 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2 476 str r1, [r0, #EMC_XM2VTTGENPADCTRL2] 477 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL 478 str r1, [r0, #EMC_AUTO_CAL_INTERVAL] 479 480 /* Relock DLL */ 481 ldr r1, [r0, #EMC_CFG_DIG_DLL] 482 orr r1, r1, #(1 << 30) @ set DLL_RESET 483 str r1, [r0, #EMC_CFG_DIG_DLL] 484 485 emc_timing_update r1, r0 486 487 cmp r10, #TEGRA114 488 movweq r1, #:lower16:TEGRA_EMC1_BASE 489 movteq r1, #:upper16:TEGRA_EMC1_BASE 490 cmpeq r0, r1 491 492 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG] 493 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE 494 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1 495 str r1, [r0, #EMC_AUTO_CAL_CONFIG] 496 497emc_wait_auto_cal_onetime: 498 ldr r1, [r0, #EMC_AUTO_CAL_STATUS] 499 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared 500 bne emc_wait_auto_cal_onetime 501 502 ldr r1, [r0, #EMC_CFG] 503 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD 504 str r1, [r0, #EMC_CFG] 505 506 mov r1, #0 507 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh 508 mov r1, #1 509 cmp r10, #TEGRA30 510 streq r1, [r0, #EMC_NOP] 511 streq r1, [r0, #EMC_NOP] 512 513 emc_device_mask r1, r0 514 515exit_selfrefresh_loop: 516 ldr r2, [r0, #EMC_EMC_STATUS] 517 ands r2, r2, r1 518 bne exit_selfrefresh_loop 519 520 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1 521 522 mov32 r7, TEGRA_TMRUS_BASE 523 ldr r2, [r0, #EMC_FBIO_CFG5] 524 525 and r2, r2, #3 @ check DRAM_TYPE 526 cmp r2, #2 527 beq emc_lpddr2 528 529 /* Issue a ZQ_CAL for dev0 - DDR3 */ 530 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1 531 str r2, [r0, #EMC_ZQ_CAL] 532 ldr r2, [r7] 533 add r2, r2, #10 534 wait_until r2, r7, r3 535 536 tst r1, #2 537 beq zcal_done 538 539 /* Issue a ZQ_CAL for dev1 - DDR3 */ 540 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1 541 str r2, [r0, #EMC_ZQ_CAL] 542 ldr r2, [r7] 543 add r2, r2, #10 544 wait_until r2, r7, r3 545 b zcal_done 546 547emc_lpddr2: 548 /* Issue a ZQ_CAL for dev0 - LPDDR2 */ 549 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB 550 str r2, [r0, #EMC_MRW] 551 ldr r2, [r7] 552 add r2, r2, #1 553 wait_until r2, r7, r3 554 555 tst r1, #2 556 beq zcal_done 557 558 /* Issue a ZQ_CAL for dev0 - LPDDR2 */ 559 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB 560 str r2, [r0, #EMC_MRW] 561 ldr r2, [r7] 562 add r2, r2, #1 563 wait_until r2, r7, r3 564 565zcal_done: 566 mov r1, #0 @ unstall all transactions 567 str r1, [r0, #EMC_REQ_CTRL] 568 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL 569 str r1, [r0, #EMC_ZCAL_INTERVAL] 570 ldr r1, [r5, #0x0] @ restore EMC_CFG 571 str r1, [r0, #EMC_CFG] 572 573 emc_timing_update r1, r0 574 575 /* Tegra114 had dual EMC channel, now config the other one */ 576 cmp r10, #TEGRA114 577 bne __no_dual_emc_chanl 578 mov32 r1, TEGRA_EMC1_BASE 579 cmp r0, r1 580 movne r0, r1 581 addne r5, r5, #0x20 582 bne exit_self_refresh 583__no_dual_emc_chanl: 584 585 mov32 r0, TEGRA_PMC_BASE 586 ldr r0, [r0, #PMC_SCRATCH41] 587 ret r0 @ jump to tegra_resume 588ENDPROC(tegra30_lp1_reset) 589 590 .align L1_CACHE_SHIFT 591tegra30_sdram_pad_address: 592 .word TEGRA_EMC_BASE + EMC_CFG @0x0 593 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 594 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 595 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc 596 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 597 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 598 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 599 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c 600tegra30_sdram_pad_address_end: 601 602tegra114_sdram_pad_address: 603 .word TEGRA_EMC0_BASE + EMC_CFG @0x0 604 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4 605 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8 606 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc 607 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 608 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 609 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 610 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c 611 .word TEGRA_EMC1_BASE + EMC_CFG @0x20 612 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24 613 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 614 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c 615 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 616tegra114_sdram_pad_adress_end: 617 618tegra124_sdram_pad_address: 619 .word TEGRA124_EMC_BASE + EMC_CFG @0x0 620 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 621 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 622 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc 623 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 624 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 625 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 626 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c 627tegra124_sdram_pad_address_end: 628 629tegra30_sdram_pad_size: 630 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address 631 632tegra114_sdram_pad_size: 633 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address 634 635 .type tegra_sdram_pad_save, %object 636tegra_sdram_pad_save: 637 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4 638 .long 0 639 .endr 640 641tegra_pll_state: 642 .word 0x0 643 644/* 645 * tegra30_tear_down_core 646 * 647 * copied into and executed from IRAM 648 * puts memory in self-refresh for LP0 and LP1 649 */ 650tegra30_tear_down_core: 651 bl tegra30_sdram_self_refresh 652 bl tegra30_switch_cpu_to_clk32k 653 b tegra30_enter_sleep 654 655/* 656 * tegra30_switch_cpu_to_clk32k 657 * 658 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK 659 * to the 32KHz clock. 660 * r4 = TEGRA_PMC_BASE 661 * r5 = TEGRA_CLK_RESET_BASE 662 * r6 = TEGRA_FLOW_CTRL_BASE 663 * r7 = TEGRA_TMRUS_BASE 664 * r10= SoC ID 665 */ 666tegra30_switch_cpu_to_clk32k: 667 /* 668 * start by jumping to CLKM to safely disable PLLs, then jump to 669 * CLKS. 670 */ 671 mov r0, #(1 << 28) 672 str r0, [r5, #CLK_RESET_SCLK_BURST] 673 /* 2uS delay delay between changing SCLK and CCLK */ 674 ldr r1, [r7] 675 add r1, r1, #2 676 wait_until r1, r7, r9 677 str r0, [r5, #CLK_RESET_CCLK_BURST] 678 mov r0, #0 679 str r0, [r5, #CLK_RESET_CCLK_DIVIDER] 680 str r0, [r5, #CLK_RESET_SCLK_DIVIDER] 681 682 /* switch the clock source of mselect to be CLK_M */ 683 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] 684 orr r0, r0, #MSELECT_CLKM 685 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] 686 687 /* 2uS delay delay between changing SCLK and disabling PLLs */ 688 ldr r1, [r7] 689 add r1, r1, #2 690 wait_until r1, r7, r9 691 692 /* store enable-state of PLLs */ 693 store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK 694 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK 695 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK 696 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK 697 store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK 698 store_pllm_pmc_state r0, r1, r4 699 700 /* disable PLLM via PMC in LP1 */ 701 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] 702 bic r0, r0, #(1 << 12) 703 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] 704 705 /* disable PLLP, PLLA, PLLC and PLLX */ 706 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 707 cmp r1, #TEGRA30 708 ldr r0, [r5, #CLK_RESET_PLLP_BASE] 709 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster 710 bic r0, r0, #(1 << 30) 711 str r0, [r5, #CLK_RESET_PLLP_BASE] 712 beq 1f 713 mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE 714 str r0, [r5, #CLK_RESET_PLLP_RESHIFT] 7151: 716 ldr r0, [r5, #CLK_RESET_PLLA_BASE] 717 bic r0, r0, #(1 << 30) 718 str r0, [r5, #CLK_RESET_PLLA_BASE] 719 ldr r0, [r5, #CLK_RESET_PLLC_BASE] 720 bic r0, r0, #(1 << 30) 721 str r0, [r5, #CLK_RESET_PLLC_BASE] 722 ldr r0, [r5, #CLK_RESET_PLLX_BASE] 723 bic r0, r0, #(1 << 30) 724 str r0, [r5, #CLK_RESET_PLLX_BASE] 725 726 cmp r10, #TEGRA30 727 beq _no_pll_in_iddq 728 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ 729_no_pll_in_iddq: 730 731 /* 732 * Switch to clk_s (32KHz); bits 28:31=0 733 * Enable burst on CPU IRQ; bit 24=1 734 * Set IRQ burst clock source to clk_m; bits 10:8=0 735 */ 736 mov r0, #(1 << 24) 737 str r0, [r5, #CLK_RESET_SCLK_BURST] 738 739 ret lr 740 741/* 742 * tegra30_enter_sleep 743 * 744 * uses flow controller to enter sleep state 745 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1 746 * executes from SDRAM with target state is LP2 747 * r6 = TEGRA_FLOW_CTRL_BASE 748 */ 749tegra30_enter_sleep: 750 cpu_id r1 751 752 cpu_to_csr_reg r2, r1 753 ldr r0, [r6, r2] 754 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG 755 orr r0, r0, #FLOW_CTRL_CSR_ENABLE 756 str r0, [r6, r2] 757 758 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 759 cmp r10, #TEGRA30 760 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT 761 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ 762 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ 763 764 cpu_to_halt_reg r2, r1 765 str r0, [r6, r2] 766 dsb 767 ldr r0, [r6, r2] /* memory barrier */ 768 769 cmp r10, #TEGRA30 770halted: 771 isb 772 dsb 773 wfine /* CPU should be power gated here */ 774 wfeeq 775 776 /* !!!FIXME!!! Implement halt failure handler */ 777 b halted 778 779/* 780 * tegra30_sdram_self_refresh 781 * 782 * called with MMU off and caches disabled 783 * must be executed from IRAM 784 * r4 = TEGRA_PMC_BASE 785 * r5 = TEGRA_CLK_RESET_BASE 786 * r6 = TEGRA_FLOW_CTRL_BASE 787 * r7 = TEGRA_TMRUS_BASE 788 * r10= SoC ID 789 */ 790tegra30_sdram_self_refresh: 791 792 adr r8, tegra_sdram_pad_save 793 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 794 cmp r10, #TEGRA30 795 adreq r2, tegra30_sdram_pad_address 796 ldreq r3, tegra30_sdram_pad_size 797 cmp r10, #TEGRA114 798 adreq r2, tegra114_sdram_pad_address 799 ldreq r3, tegra114_sdram_pad_size 800 cmp r10, #TEGRA124 801 adreq r2, tegra124_sdram_pad_address 802 ldreq r3, tegra30_sdram_pad_size 803 804 mov r9, #0 805 806padsave: 807 ldr r0, [r2, r9] @ r0 is the addr in the pad_address 808 809 ldr r1, [r0] 810 str r1, [r8, r9] @ save the content of the addr 811 812 add r9, r9, #4 813 cmp r3, r9 814 bne padsave 815padsave_done: 816 817 dsb 818 819 cmp r10, #TEGRA30 820 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr 821 cmp r10, #TEGRA114 822 ldreq r0, =TEGRA_EMC0_BASE 823 cmp r10, #TEGRA124 824 ldreq r0, =TEGRA124_EMC_BASE 825 826enter_self_refresh: 827 cmp r10, #TEGRA30 828 mov r1, #0 829 str r1, [r0, #EMC_ZCAL_INTERVAL] 830 str r1, [r0, #EMC_AUTO_CAL_INTERVAL] 831 ldr r1, [r0, #EMC_CFG] 832 bic r1, r1, #(1 << 28) 833 bicne r1, r1, #(1 << 29) 834 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF 835 836 emc_timing_update r1, r0 837 838 ldr r1, [r7] 839 add r1, r1, #5 840 wait_until r1, r7, r2 841 842emc_wait_auto_cal: 843 ldr r1, [r0, #EMC_AUTO_CAL_STATUS] 844 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared 845 bne emc_wait_auto_cal 846 847 mov r1, #3 848 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests 849 850emcidle: 851 ldr r1, [r0, #EMC_EMC_STATUS] 852 tst r1, #4 853 beq emcidle 854 855 mov r1, #1 856 str r1, [r0, #EMC_SELF_REF] 857 858 emc_device_mask r1, r0 859 860emcself: 861 ldr r2, [r0, #EMC_EMC_STATUS] 862 and r2, r2, r1 863 cmp r2, r1 864 bne emcself @ loop until DDR in self-refresh 865 866 /* Put VTTGEN in the lowest power mode */ 867 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL] 868 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN 869 and r1, r1, r2 870 str r1, [r0, #EMC_XM2VTTGENPADCTRL] 871 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2] 872 cmp r10, #TEGRA30 873 orreq r1, r1, #7 @ set E_NO_VTTGEN 874 orrne r1, r1, #0x3f 875 str r1, [r0, #EMC_XM2VTTGENPADCTRL2] 876 877 emc_timing_update r1, r0 878 879 /* Tegra114 had dual EMC channel, now config the other one */ 880 cmp r10, #TEGRA114 881 bne no_dual_emc_chanl 882 mov32 r1, TEGRA_EMC1_BASE 883 cmp r0, r1 884 movne r0, r1 885 bne enter_self_refresh 886no_dual_emc_chanl: 887 888 ldr r1, [r4, #PMC_CTRL] 889 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0 890 bne pmc_io_dpd_skip 891 /* 892 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK 893 * and COMP in the lowest power mode when LP1. 894 */ 895 mov32 r1, 0x8EC00000 896 str r1, [r4, #PMC_IO_DPD_REQ] 897pmc_io_dpd_skip: 898 899 dsb 900 901 ret lr 902 903 .ltorg 904/* dummy symbol for end of IRAM */ 905 .align L1_CACHE_SHIFT 906 .global tegra30_iram_end 907tegra30_iram_end: 908 b . 909#endif 910