1 /* 2 * arch/arm/mach-tegra/reset.h 3 * 4 * CPU reset dispatcher. 5 * 6 * Copyright (c) 2011, NVIDIA Corporation. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __MACH_TEGRA_RESET_H 20 #define __MACH_TEGRA_RESET_H 21 22 #define TEGRA_RESET_MASK_PRESENT 0 23 #define TEGRA_RESET_MASK_LP1 1 24 #define TEGRA_RESET_MASK_LP2 2 25 #define TEGRA_RESET_STARTUP_SECONDARY 3 26 #define TEGRA_RESET_STARTUP_LP2 4 27 #define TEGRA_RESET_STARTUP_LP1 5 28 #define TEGRA_RESET_DATA_SIZE 6 29 30 #ifndef __ASSEMBLY__ 31 32 #include "irammap.h" 33 34 extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]; 35 36 void __tegra_cpu_reset_handler_start(void); 37 void __tegra_cpu_reset_handler(void); 38 void __tegra_cpu_reset_handler_end(void); 39 void tegra_secondary_startup(void); 40 41 #ifdef CONFIG_PM_SLEEP 42 #define tegra_cpu_lp1_mask \ 43 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 44 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \ 45 (u32)__tegra_cpu_reset_handler_start))) 46 #define tegra_cpu_lp2_mask \ 47 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 48 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ 49 (u32)__tegra_cpu_reset_handler_start))) 50 #endif 51 52 #define tegra_cpu_reset_handler_offset \ 53 ((u32)__tegra_cpu_reset_handler - \ 54 (u32)__tegra_cpu_reset_handler_start) 55 56 #define tegra_cpu_reset_handler_size \ 57 (__tegra_cpu_reset_handler_end - \ 58 __tegra_cpu_reset_handler_start) 59 60 void __init tegra_cpu_reset_handler_init(void); 61 62 #endif 63 #endif 64