1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/mach-tegra/reset.h 4 * 5 * CPU reset dispatcher. 6 * 7 * Copyright (c) 2011, NVIDIA Corporation. 8 */ 9 10 #ifndef __MACH_TEGRA_RESET_H 11 #define __MACH_TEGRA_RESET_H 12 13 #define TEGRA_RESET_MASK_PRESENT 0 14 #define TEGRA_RESET_MASK_LP1 1 15 #define TEGRA_RESET_MASK_LP2 2 16 #define TEGRA_RESET_STARTUP_SECONDARY 3 17 #define TEGRA_RESET_STARTUP_LP2 4 18 #define TEGRA_RESET_STARTUP_LP1 5 19 #define TEGRA_RESET_RESETTABLE_STATUS 6 20 #define TEGRA_RESET_TF_PRESENT 7 21 #define TEGRA_RESET_DATA_SIZE 8 22 23 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) 24 25 #ifndef __ASSEMBLY__ 26 27 #include "irammap.h" 28 29 extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]; 30 31 void __tegra_cpu_reset_handler_start(void); 32 void __tegra_cpu_reset_handler(void); 33 void __tegra20_cpu1_resettable_status_offset(void); 34 void __tegra_cpu_reset_handler_end(void); 35 36 #ifdef CONFIG_PM_SLEEP 37 #define tegra_cpu_lp1_mask \ 38 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 39 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \ 40 (u32)__tegra_cpu_reset_handler_start))) 41 #define tegra_cpu_lp2_mask \ 42 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 43 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ 44 (u32)__tegra_cpu_reset_handler_start))) 45 #define tegra20_cpu1_resettable_status \ 46 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 47 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \ 48 (u32)__tegra_cpu_reset_handler_start))) 49 #endif 50 51 #define tegra_cpu_reset_handler_offset \ 52 ((u32)__tegra_cpu_reset_handler - \ 53 (u32)__tegra_cpu_reset_handler_start) 54 55 #define tegra_cpu_reset_handler_size \ 56 (__tegra_cpu_reset_handler_end - \ 57 __tegra_cpu_reset_handler_start) 58 59 void __init tegra_cpu_reset_handler_init(void); 60 61 #endif 62 #endif 63