1 /* 2 * arch/arm/mach-tegra/reset.c 3 * 4 * Copyright (C) 2011,2012 NVIDIA Corporation. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/bitops.h> 18 #include <linux/cpumask.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 22 #include <linux/firmware/trusted_foundations.h> 23 24 #include <soc/tegra/fuse.h> 25 26 #include <asm/cacheflush.h> 27 #include <asm/firmware.h> 28 #include <asm/hardware/cache-l2x0.h> 29 30 #include "iomap.h" 31 #include "irammap.h" 32 #include "reset.h" 33 #include "sleep.h" 34 35 #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \ 36 TEGRA_IRAM_RESET_HANDLER_OFFSET) 37 38 static bool is_enabled; 39 40 static void __init tegra_cpu_reset_handler_set(const u32 reset_address) 41 { 42 void __iomem *evp_cpu_reset = 43 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); 44 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); 45 u32 reg; 46 47 /* 48 * NOTE: This must be the one and only write to the EVP CPU reset 49 * vector in the entire system. 50 */ 51 writel(reset_address, evp_cpu_reset); 52 wmb(); 53 reg = readl(evp_cpu_reset); 54 55 /* 56 * Prevent further modifications to the physical reset vector. 57 * NOTE: Has no effect on chips prior to Tegra30. 58 */ 59 reg = readl(sb_ctrl); 60 reg |= 2; 61 writel(reg, sb_ctrl); 62 wmb(); 63 } 64 65 static void __init tegra_cpu_reset_handler_enable(void) 66 { 67 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); 68 const u32 reset_address = TEGRA_IRAM_RESET_BASE + 69 tegra_cpu_reset_handler_offset; 70 int err; 71 72 BUG_ON(is_enabled); 73 BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); 74 75 memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, 76 tegra_cpu_reset_handler_size); 77 78 err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); 79 switch (err) { 80 case -ENOSYS: 81 tegra_cpu_reset_handler_set(reset_address); 82 /* pass-through */ 83 case 0: 84 is_enabled = true; 85 break; 86 default: 87 pr_crit("Cannot set CPU reset handler: %d\n", err); 88 BUG(); 89 } 90 } 91 92 void __init tegra_cpu_reset_handler_init(void) 93 { 94 __tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] = 95 trusted_foundations_registered(); 96 97 #ifdef CONFIG_SMP 98 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = 99 *((u32 *)cpu_possible_mask); 100 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = 101 __pa_symbol((void *)secondary_startup); 102 #endif 103 104 #ifdef CONFIG_PM_SLEEP 105 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = 106 TEGRA_IRAM_LPx_RESUME_AREA; 107 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = 108 __pa_symbol((void *)tegra_resume); 109 #endif 110 111 tegra_cpu_reset_handler_enable(); 112 } 113