1 /* 2 * arch/arm/mach-tegra/reset.c 3 * 4 * Copyright (C) 2011,2012 NVIDIA Corporation. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/bitops.h> 18 #include <linux/cpumask.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 22 #include <soc/tegra/fuse.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/firmware.h> 26 #include <asm/hardware/cache-l2x0.h> 27 #include <asm/trusted_foundations.h> 28 29 #include "iomap.h" 30 #include "irammap.h" 31 #include "reset.h" 32 #include "sleep.h" 33 34 #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \ 35 TEGRA_IRAM_RESET_HANDLER_OFFSET) 36 37 static bool is_enabled; 38 39 static void __init tegra_cpu_reset_handler_set(const u32 reset_address) 40 { 41 void __iomem *evp_cpu_reset = 42 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); 43 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); 44 u32 reg; 45 46 /* 47 * NOTE: This must be the one and only write to the EVP CPU reset 48 * vector in the entire system. 49 */ 50 writel(reset_address, evp_cpu_reset); 51 wmb(); 52 reg = readl(evp_cpu_reset); 53 54 /* 55 * Prevent further modifications to the physical reset vector. 56 * NOTE: Has no effect on chips prior to Tegra30. 57 */ 58 reg = readl(sb_ctrl); 59 reg |= 2; 60 writel(reg, sb_ctrl); 61 wmb(); 62 } 63 64 static void __init tegra_cpu_reset_handler_enable(void) 65 { 66 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); 67 const u32 reset_address = TEGRA_IRAM_RESET_BASE + 68 tegra_cpu_reset_handler_offset; 69 int err; 70 71 BUG_ON(is_enabled); 72 BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); 73 74 memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, 75 tegra_cpu_reset_handler_size); 76 77 err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); 78 switch (err) { 79 case -ENOSYS: 80 tegra_cpu_reset_handler_set(reset_address); 81 /* pass-through */ 82 case 0: 83 is_enabled = true; 84 break; 85 default: 86 pr_crit("Cannot set CPU reset handler: %d\n", err); 87 BUG(); 88 } 89 } 90 91 void __init tegra_cpu_reset_handler_init(void) 92 { 93 __tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] = 94 trusted_foundations_registered(); 95 96 #ifdef CONFIG_SMP 97 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = 98 *((u32 *)cpu_possible_mask); 99 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = 100 __pa_symbol((void *)secondary_startup); 101 #endif 102 103 #ifdef CONFIG_PM_SLEEP 104 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = 105 TEGRA_IRAM_LPx_RESUME_AREA; 106 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = 107 __pa_symbol((void *)tegra_resume); 108 #endif 109 110 tegra_cpu_reset_handler_enable(); 111 } 112