1/* 2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/init.h> 18#include <linux/linkage.h> 19 20#include <soc/tegra/fuse.h> 21 22#include <asm/asm-offsets.h> 23#include <asm/cache.h> 24 25#include "flowctrl.h" 26#include "iomap.h" 27#include "reset.h" 28#include "sleep.h" 29 30#define PMC_SCRATCH41 0x140 31 32#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) 33 34#ifdef CONFIG_PM_SLEEP 35/* 36 * tegra_resume 37 * 38 * CPU boot vector when restarting the a CPU following 39 * an LP2 transition. Also branched to by LP0 and LP1 resume after 40 * re-enabling sdram. 41 * 42 * r6: SoC ID 43 * r8: CPU part number 44 */ 45ENTRY(tegra_resume) 46 check_cpu_part_num 0xc09, r8, r9 47 bleq v7_invalidate_l1 48 49 cpu_id r0 50 cmp r0, #0 @ CPU0? 51 THUMB( it ne ) 52 bne cpu_resume @ no 53 54 /* Are we on Tegra20? */ 55 cmp r6, #TEGRA20 56 beq 1f @ Yes 57 /* Clear the flow controller flags for this CPU. */ 58 cpu_to_csr_reg r1, r0 59 mov32 r2, TEGRA_FLOW_CTRL_BASE 60 ldr r1, [r2, r1] 61 /* Clear event & intr flag */ 62 orr r1, r1, \ 63 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG 64 movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps 65 @ & ext flags for CPU power mgnt 66 bic r1, r1, r0 67 str r1, [r2] 681: 69 70 mov32 r9, 0xc09 71 cmp r8, r9 72 bne end_ca9_scu_l2_resume 73#ifdef CONFIG_HAVE_ARM_SCU 74 /* enable SCU */ 75 mov32 r0, TEGRA_ARM_PERIF_BASE 76 ldr r1, [r0] 77 orr r1, r1, #1 78 str r1, [r0] 79#endif 80 81#ifdef CONFIG_CACHE_L2X0 82 /* L2 cache resume & re-enable */ 83 bl l2c310_early_resume 84#endif 85end_ca9_scu_l2_resume: 86 mov32 r9, 0xc0f 87 cmp r8, r9 88 bleq tegra_init_l2_for_a15 89 90 b cpu_resume 91ENDPROC(tegra_resume) 92#endif 93 94 .align L1_CACHE_SHIFT 95ENTRY(__tegra_cpu_reset_handler_start) 96 97/* 98 * __tegra_cpu_reset_handler: 99 * 100 * Common handler for all CPU reset events. 101 * 102 * Register usage within the reset handler: 103 * 104 * Others: scratch 105 * R6 = SoC ID 106 * R7 = CPU present (to the OS) mask 107 * R8 = CPU in LP1 state mask 108 * R9 = CPU in LP2 state mask 109 * R10 = CPU number 110 * R11 = CPU mask 111 * R12 = pointer to reset handler data 112 * 113 * NOTE: This code is copied to IRAM. All code and data accesses 114 * must be position-independent. 115 */ 116 117 .align L1_CACHE_SHIFT 118ENTRY(__tegra_cpu_reset_handler) 119 120 cpsid aif, 0x13 @ SVC mode, interrupts disabled 121 122 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 123#ifdef CONFIG_ARCH_TEGRA_2x_SOC 124t20_check: 125 cmp r6, #TEGRA20 126 bne after_t20_check 127t20_errata: 128 # Tegra20 is a Cortex-A9 r1p1 129 mrc p15, 0, r0, c1, c0, 0 @ read system control register 130 orr r0, r0, #1 << 14 @ erratum 716044 131 mcr p15, 0, r0, c1, c0, 0 @ write system control register 132 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 133 orr r0, r0, #1 << 4 @ erratum 742230 134 orr r0, r0, #1 << 11 @ erratum 751472 135 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 136 b after_errata 137after_t20_check: 138#endif 139#ifdef CONFIG_ARCH_TEGRA_3x_SOC 140t30_check: 141 cmp r6, #TEGRA30 142 bne after_t30_check 143t30_errata: 144 # Tegra30 is a Cortex-A9 r2p9 145 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 146 orr r0, r0, #1 << 6 @ erratum 743622 147 orr r0, r0, #1 << 11 @ erratum 751472 148 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 149 b after_errata 150after_t30_check: 151#endif 152after_errata: 153 mrc p15, 0, r10, c0, c0, 5 @ MPIDR 154 and r10, r10, #0x3 @ R10 = CPU number 155 mov r11, #1 156 mov r11, r11, lsl r10 @ R11 = CPU mask 157 adr r12, __tegra_cpu_reset_handler_data 158 159#ifdef CONFIG_SMP 160 /* Does the OS know about this CPU? */ 161 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)] 162 tst r7, r11 @ if !present 163 bleq __die @ CPU not present (to OS) 164#endif 165 166#ifdef CONFIG_ARCH_TEGRA_2x_SOC 167 /* Are we on Tegra20? */ 168 cmp r6, #TEGRA20 169 bne 1f 170 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ 171 mov32 r5, TEGRA_PMC_BASE 172 mov r0, #0 173 cmp r10, #0 174 strne r0, [r5, #PMC_SCRATCH41] 1751: 176#endif 177 178 /* Waking up from LP1? */ 179 ldr r8, [r12, #RESET_DATA(MASK_LP1)] 180 tst r8, r11 @ if in_lp1 181 beq __is_not_lp1 182 cmp r10, #0 183 bne __die @ only CPU0 can be here 184 ldr lr, [r12, #RESET_DATA(STARTUP_LP1)] 185 cmp lr, #0 186 bleq __die @ no LP1 startup handler 187 THUMB( add lr, lr, #1 ) @ switch to Thumb mode 188 bx lr 189__is_not_lp1: 190 191 /* Waking up from LP2? */ 192 ldr r9, [r12, #RESET_DATA(MASK_LP2)] 193 tst r9, r11 @ if in_lp2 194 beq __is_not_lp2 195 ldr lr, [r12, #RESET_DATA(STARTUP_LP2)] 196 cmp lr, #0 197 bleq __die @ no LP2 startup handler 198 bx lr 199 200__is_not_lp2: 201 202#ifdef CONFIG_SMP 203 /* 204 * Can only be secondary boot (initial or hotplug) 205 * CPU0 can't be here for Tegra20/30 206 */ 207 cmp r6, #TEGRA114 208 beq __no_cpu0_chk 209 cmp r10, #0 210 bleq __die @ CPU0 cannot be here 211__no_cpu0_chk: 212 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)] 213 cmp lr, #0 214 bleq __die @ no secondary startup handler 215 bx lr 216#endif 217 218/* 219 * We don't know why the CPU reset. Just kill it. 220 * The LR register will contain the address we died at + 4. 221 */ 222 223__die: 224 sub lr, lr, #4 225 mov32 r7, TEGRA_PMC_BASE 226 str lr, [r7, #PMC_SCRATCH41] 227 228 mov32 r7, TEGRA_CLK_RESET_BASE 229 230 /* Are we on Tegra20? */ 231 cmp r6, #TEGRA20 232 bne 1f 233 234#ifdef CONFIG_ARCH_TEGRA_2x_SOC 235 mov32 r0, 0x1111 236 mov r1, r0, lsl r10 237 str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET 238#endif 2391: 240#ifdef CONFIG_ARCH_TEGRA_3x_SOC 241 mov32 r6, TEGRA_FLOW_CTRL_BASE 242 243 cmp r10, #0 244 moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS 245 moveq r2, #FLOW_CTRL_CPU0_CSR 246 movne r1, r10, lsl #3 247 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8) 248 addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8) 249 250 /* Clear CPU "event" and "interrupt" flags and power gate 251 it when halting but not before it is in the "WFI" state. */ 252 ldr r0, [r6, +r2] 253 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG 254 orr r0, r0, #FLOW_CTRL_CSR_ENABLE 255 str r0, [r6, +r2] 256 257 /* Unconditionally halt this CPU */ 258 mov r0, #FLOW_CTRL_WAITEVENT 259 str r0, [r6, +r1] 260 ldr r0, [r6, +r1] @ memory barrier 261 262 dsb 263 isb 264 wfi @ CPU should be power gated here 265 266 /* If the CPU didn't power gate above just kill it's clock. */ 267 268 mov r0, r11, lsl #8 269 str r0, [r7, #348] @ CLK_CPU_CMPLX_SET 270#endif 271 272 /* If the CPU still isn't dead, just spin here. */ 273 b . 274ENDPROC(__tegra_cpu_reset_handler) 275 276 .align L1_CACHE_SHIFT 277 .type __tegra_cpu_reset_handler_data, %object 278 .globl __tegra_cpu_reset_handler_data 279__tegra_cpu_reset_handler_data: 280 .rept TEGRA_RESET_DATA_SIZE 281 .long 0 282 .endr 283 .align L1_CACHE_SHIFT 284 285ENTRY(__tegra_cpu_reset_handler_end) 286