1 /* 2 * CPU complex suspend & resume functions for Tegra SoCs 3 * 4 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 #include <linux/cpumask.h> 23 #include <linux/delay.h> 24 #include <linux/cpu_pm.h> 25 #include <linux/suspend.h> 26 #include <linux/err.h> 27 #include <linux/slab.h> 28 #include <linux/clk/tegra.h> 29 30 #include <asm/smp_plat.h> 31 #include <asm/cacheflush.h> 32 #include <asm/suspend.h> 33 #include <asm/idmap.h> 34 #include <asm/proc-fns.h> 35 #include <asm/tlbflush.h> 36 37 #include "iomap.h" 38 #include "reset.h" 39 #include "flowctrl.h" 40 #include "fuse.h" 41 #include "pm.h" 42 #include "pmc.h" 43 #include "sleep.h" 44 45 #ifdef CONFIG_PM_SLEEP 46 static DEFINE_SPINLOCK(tegra_lp2_lock); 47 static u32 iram_save_size; 48 static void *iram_save_addr; 49 struct tegra_lp1_iram tegra_lp1_iram; 50 void (*tegra_tear_down_cpu)(void); 51 void (*tegra_sleep_core_finish)(unsigned long v2p); 52 static int (*tegra_sleep_func)(unsigned long v2p); 53 54 static void tegra_tear_down_cpu_init(void) 55 { 56 switch (tegra_chip_id) { 57 case TEGRA20: 58 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 59 tegra_tear_down_cpu = tegra20_tear_down_cpu; 60 break; 61 case TEGRA30: 62 case TEGRA114: 63 case TEGRA124: 64 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 65 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 66 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 67 tegra_tear_down_cpu = tegra30_tear_down_cpu; 68 break; 69 } 70 } 71 72 /* 73 * restore_cpu_complex 74 * 75 * restores cpu clock setting, clears flow controller 76 * 77 * Always called on CPU 0. 78 */ 79 static void restore_cpu_complex(void) 80 { 81 int cpu = smp_processor_id(); 82 83 BUG_ON(cpu != 0); 84 85 #ifdef CONFIG_SMP 86 cpu = cpu_logical_map(cpu); 87 #endif 88 89 /* Restore the CPU clock settings */ 90 tegra_cpu_clock_resume(); 91 92 flowctrl_cpu_suspend_exit(cpu); 93 } 94 95 /* 96 * suspend_cpu_complex 97 * 98 * saves pll state for use by restart_plls, prepares flow controller for 99 * transition to suspend state 100 * 101 * Must always be called on cpu 0. 102 */ 103 static void suspend_cpu_complex(void) 104 { 105 int cpu = smp_processor_id(); 106 107 BUG_ON(cpu != 0); 108 109 #ifdef CONFIG_SMP 110 cpu = cpu_logical_map(cpu); 111 #endif 112 113 /* Save the CPU clock settings */ 114 tegra_cpu_clock_suspend(); 115 116 flowctrl_cpu_suspend_enter(cpu); 117 } 118 119 void tegra_clear_cpu_in_lp2(void) 120 { 121 int phy_cpu_id = cpu_logical_map(smp_processor_id()); 122 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 123 124 spin_lock(&tegra_lp2_lock); 125 126 BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id))); 127 *cpu_in_lp2 &= ~BIT(phy_cpu_id); 128 129 spin_unlock(&tegra_lp2_lock); 130 } 131 132 bool tegra_set_cpu_in_lp2(void) 133 { 134 int phy_cpu_id = cpu_logical_map(smp_processor_id()); 135 bool last_cpu = false; 136 cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; 137 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 138 139 spin_lock(&tegra_lp2_lock); 140 141 BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); 142 *cpu_in_lp2 |= BIT(phy_cpu_id); 143 144 if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) 145 last_cpu = true; 146 else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1) 147 tegra20_cpu_set_resettable_soon(); 148 149 spin_unlock(&tegra_lp2_lock); 150 return last_cpu; 151 } 152 153 int tegra_cpu_do_idle(void) 154 { 155 return cpu_do_idle(); 156 } 157 158 static int tegra_sleep_cpu(unsigned long v2p) 159 { 160 setup_mm_for_reboot(); 161 tegra_sleep_cpu_finish(v2p); 162 163 /* should never here */ 164 BUG(); 165 166 return 0; 167 } 168 169 void tegra_idle_lp2_last(void) 170 { 171 tegra_pmc_pm_set(TEGRA_SUSPEND_LP2); 172 173 cpu_cluster_pm_enter(); 174 suspend_cpu_complex(); 175 176 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 177 178 restore_cpu_complex(); 179 cpu_cluster_pm_exit(); 180 } 181 182 enum tegra_suspend_mode tegra_pm_validate_suspend_mode( 183 enum tegra_suspend_mode mode) 184 { 185 /* 186 * The Tegra devices support suspending to LP1 or lower currently. 187 */ 188 if (mode > TEGRA_SUSPEND_LP1) 189 return TEGRA_SUSPEND_LP1; 190 191 return mode; 192 } 193 194 static int tegra_sleep_core(unsigned long v2p) 195 { 196 setup_mm_for_reboot(); 197 tegra_sleep_core_finish(v2p); 198 199 /* should never here */ 200 BUG(); 201 202 return 0; 203 } 204 205 /* 206 * tegra_lp1_iram_hook 207 * 208 * Hooking the address of LP1 reset vector and SDRAM self-refresh code in 209 * SDRAM. These codes not be copied to IRAM in this fuction. We need to 210 * copy these code to IRAM before LP0/LP1 suspend and restore the content 211 * of IRAM after resume. 212 */ 213 static bool tegra_lp1_iram_hook(void) 214 { 215 switch (tegra_chip_id) { 216 case TEGRA20: 217 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 218 tegra20_lp1_iram_hook(); 219 break; 220 case TEGRA30: 221 case TEGRA114: 222 case TEGRA124: 223 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 224 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 225 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 226 tegra30_lp1_iram_hook(); 227 break; 228 default: 229 break; 230 } 231 232 if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr) 233 return false; 234 235 iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr; 236 iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL); 237 if (!iram_save_addr) 238 return false; 239 240 return true; 241 } 242 243 static bool tegra_sleep_core_init(void) 244 { 245 switch (tegra_chip_id) { 246 case TEGRA20: 247 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 248 tegra20_sleep_core_init(); 249 break; 250 case TEGRA30: 251 case TEGRA114: 252 case TEGRA124: 253 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 254 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 255 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 256 tegra30_sleep_core_init(); 257 break; 258 default: 259 break; 260 } 261 262 if (!tegra_sleep_core_finish) 263 return false; 264 265 return true; 266 } 267 268 static void tegra_suspend_enter_lp1(void) 269 { 270 tegra_pmc_suspend(); 271 272 /* copy the reset vector & SDRAM shutdown code into IRAM */ 273 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), 274 iram_save_size); 275 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), 276 tegra_lp1_iram.start_addr, iram_save_size); 277 278 *((u32 *)tegra_cpu_lp1_mask) = 1; 279 } 280 281 static void tegra_suspend_exit_lp1(void) 282 { 283 tegra_pmc_resume(); 284 285 /* restore IRAM */ 286 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, 287 iram_save_size); 288 289 *(u32 *)tegra_cpu_lp1_mask = 0; 290 } 291 292 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { 293 [TEGRA_SUSPEND_NONE] = "none", 294 [TEGRA_SUSPEND_LP2] = "LP2", 295 [TEGRA_SUSPEND_LP1] = "LP1", 296 [TEGRA_SUSPEND_LP0] = "LP0", 297 }; 298 299 static int tegra_suspend_enter(suspend_state_t state) 300 { 301 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); 302 303 if (WARN_ON(mode < TEGRA_SUSPEND_NONE || 304 mode >= TEGRA_MAX_SUSPEND_MODE)) 305 return -EINVAL; 306 307 pr_info("Entering suspend state %s\n", lp_state[mode]); 308 309 tegra_pmc_pm_set(mode); 310 311 local_fiq_disable(); 312 313 suspend_cpu_complex(); 314 switch (mode) { 315 case TEGRA_SUSPEND_LP1: 316 tegra_suspend_enter_lp1(); 317 break; 318 case TEGRA_SUSPEND_LP2: 319 tegra_set_cpu_in_lp2(); 320 break; 321 default: 322 break; 323 } 324 325 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func); 326 327 switch (mode) { 328 case TEGRA_SUSPEND_LP1: 329 tegra_suspend_exit_lp1(); 330 break; 331 case TEGRA_SUSPEND_LP2: 332 tegra_clear_cpu_in_lp2(); 333 break; 334 default: 335 break; 336 } 337 restore_cpu_complex(); 338 339 local_fiq_enable(); 340 341 return 0; 342 } 343 344 static const struct platform_suspend_ops tegra_suspend_ops = { 345 .valid = suspend_valid_only_mem, 346 .enter = tegra_suspend_enter, 347 }; 348 349 void __init tegra_init_suspend(void) 350 { 351 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); 352 353 if (mode == TEGRA_SUSPEND_NONE) 354 return; 355 356 tegra_tear_down_cpu_init(); 357 tegra_pmc_suspend_init(); 358 359 if (mode >= TEGRA_SUSPEND_LP1) { 360 if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { 361 pr_err("%s: unable to allocate memory for SDRAM" 362 "self-refresh -- LP0/LP1 unavailable\n", 363 __func__); 364 tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2); 365 mode = TEGRA_SUSPEND_LP2; 366 } 367 } 368 369 /* set up sleep function for cpu_suspend */ 370 switch (mode) { 371 case TEGRA_SUSPEND_LP1: 372 tegra_sleep_func = tegra_sleep_core; 373 break; 374 case TEGRA_SUSPEND_LP2: 375 tegra_sleep_func = tegra_sleep_cpu; 376 break; 377 default: 378 break; 379 } 380 381 suspend_set_ops(&tegra_suspend_ops); 382 } 383 #endif 384