19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2d457ef35SJoseph Lo /* 3d457ef35SJoseph Lo * CPU complex suspend & resume functions for Tegra SoCs 4d457ef35SJoseph Lo * 5d457ef35SJoseph Lo * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. 6d457ef35SJoseph Lo */ 7d457ef35SJoseph Lo 889572c77SPrashant Gaikwad #include <linux/clk/tegra.h> 9a0524accSThierry Reding #include <linux/cpumask.h> 10a0524accSThierry Reding #include <linux/cpu_pm.h> 11a0524accSThierry Reding #include <linux/delay.h> 12a0524accSThierry Reding #include <linux/err.h> 13a0524accSThierry Reding #include <linux/io.h> 14a0524accSThierry Reding #include <linux/kernel.h> 15a0524accSThierry Reding #include <linux/slab.h> 16a0524accSThierry Reding #include <linux/spinlock.h> 17a0524accSThierry Reding #include <linux/suspend.h> 18d552920aSJoseph Lo 194cb5d9ecSThierry Reding #include <linux/firmware/trusted_foundations.h> 204cb5d9ecSThierry Reding 217e10cf74SJon Hunter #include <soc/tegra/flowctrl.h> 22304664eaSThierry Reding #include <soc/tegra/fuse.h> 237232398aSThierry Reding #include <soc/tegra/pm.h> 247232398aSThierry Reding #include <soc/tegra/pmc.h> 25304664eaSThierry Reding 26d552920aSJoseph Lo #include <asm/cacheflush.h> 2778ee399fSDmitry Osipenko #include <asm/firmware.h> 28d552920aSJoseph Lo #include <asm/idmap.h> 29d552920aSJoseph Lo #include <asm/proc-fns.h> 30a0524accSThierry Reding #include <asm/smp_plat.h> 31a0524accSThierry Reding #include <asm/suspend.h> 32d552920aSJoseph Lo #include <asm/tlbflush.h> 33d457ef35SJoseph Lo 34a0524accSThierry Reding #include "iomap.h" 35a0524accSThierry Reding #include "pm.h" 36a0524accSThierry Reding #include "reset.h" 37d552920aSJoseph Lo #include "sleep.h" 38d552920aSJoseph Lo 39d457ef35SJoseph Lo #ifdef CONFIG_PM_SLEEP 40d457ef35SJoseph Lo static DEFINE_SPINLOCK(tegra_lp2_lock); 4195872f42SJoseph Lo static u32 iram_save_size; 4295872f42SJoseph Lo static void *iram_save_addr; 4395872f42SJoseph Lo struct tegra_lp1_iram tegra_lp1_iram; 44d552920aSJoseph Lo void (*tegra_tear_down_cpu)(void); 4595872f42SJoseph Lo void (*tegra_sleep_core_finish)(unsigned long v2p); 4695872f42SJoseph Lo static int (*tegra_sleep_func)(unsigned long v2p); 47d457ef35SJoseph Lo 48bf91add4SJoseph Lo static void tegra_tear_down_cpu_init(void) 49bf91add4SJoseph Lo { 50304664eaSThierry Reding switch (tegra_get_chip_id()) { 51bf91add4SJoseph Lo case TEGRA20: 52bf91add4SJoseph Lo if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 53bf91add4SJoseph Lo tegra_tear_down_cpu = tegra20_tear_down_cpu; 54bf91add4SJoseph Lo break; 55bf91add4SJoseph Lo case TEGRA30: 56b573ad9fSJoseph Lo case TEGRA114: 57f0c4ac13SJoseph Lo case TEGRA124: 58b573ad9fSJoseph Lo if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 59f0c4ac13SJoseph Lo IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 60f0c4ac13SJoseph Lo IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 61bf91add4SJoseph Lo tegra_tear_down_cpu = tegra30_tear_down_cpu; 62bf91add4SJoseph Lo break; 63bf91add4SJoseph Lo } 64bf91add4SJoseph Lo } 65bf91add4SJoseph Lo 66d552920aSJoseph Lo /* 67d552920aSJoseph Lo * restore_cpu_complex 68d552920aSJoseph Lo * 69d552920aSJoseph Lo * restores cpu clock setting, clears flow controller 70d552920aSJoseph Lo * 71d552920aSJoseph Lo * Always called on CPU 0. 72d552920aSJoseph Lo */ 73d552920aSJoseph Lo static void restore_cpu_complex(void) 74d552920aSJoseph Lo { 75d552920aSJoseph Lo int cpu = smp_processor_id(); 76d552920aSJoseph Lo 77d552920aSJoseph Lo BUG_ON(cpu != 0); 78d552920aSJoseph Lo 79d552920aSJoseph Lo #ifdef CONFIG_SMP 80d552920aSJoseph Lo cpu = cpu_logical_map(cpu); 81d552920aSJoseph Lo #endif 82d552920aSJoseph Lo 83d552920aSJoseph Lo /* Restore the CPU clock settings */ 84d552920aSJoseph Lo tegra_cpu_clock_resume(); 85d552920aSJoseph Lo 86d552920aSJoseph Lo flowctrl_cpu_suspend_exit(cpu); 87d552920aSJoseph Lo } 88d552920aSJoseph Lo 89d552920aSJoseph Lo /* 90d552920aSJoseph Lo * suspend_cpu_complex 91d552920aSJoseph Lo * 92d552920aSJoseph Lo * saves pll state for use by restart_plls, prepares flow controller for 93d552920aSJoseph Lo * transition to suspend state 94d552920aSJoseph Lo * 95d552920aSJoseph Lo * Must always be called on cpu 0. 96d552920aSJoseph Lo */ 97d552920aSJoseph Lo static void suspend_cpu_complex(void) 98d552920aSJoseph Lo { 99d552920aSJoseph Lo int cpu = smp_processor_id(); 100d552920aSJoseph Lo 101d552920aSJoseph Lo BUG_ON(cpu != 0); 102d552920aSJoseph Lo 103d552920aSJoseph Lo #ifdef CONFIG_SMP 104d552920aSJoseph Lo cpu = cpu_logical_map(cpu); 105d552920aSJoseph Lo #endif 106d552920aSJoseph Lo 107d552920aSJoseph Lo /* Save the CPU clock settings */ 108d552920aSJoseph Lo tegra_cpu_clock_suspend(); 109d552920aSJoseph Lo 110d552920aSJoseph Lo flowctrl_cpu_suspend_enter(cpu); 111d552920aSJoseph Lo } 112d552920aSJoseph Lo 113*1f3e18ecSDmitry Osipenko void tegra_pm_clear_cpu_in_lp2(void) 114d457ef35SJoseph Lo { 1158f6a0b65SJoseph Lo int phy_cpu_id = cpu_logical_map(smp_processor_id()); 116d457ef35SJoseph Lo u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 117d457ef35SJoseph Lo 118d457ef35SJoseph Lo spin_lock(&tegra_lp2_lock); 119d457ef35SJoseph Lo 120d457ef35SJoseph Lo BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id))); 121d457ef35SJoseph Lo *cpu_in_lp2 &= ~BIT(phy_cpu_id); 122d457ef35SJoseph Lo 123d457ef35SJoseph Lo spin_unlock(&tegra_lp2_lock); 124d457ef35SJoseph Lo } 125d457ef35SJoseph Lo 126*1f3e18ecSDmitry Osipenko void tegra_pm_set_cpu_in_lp2(void) 127d457ef35SJoseph Lo { 1288f6a0b65SJoseph Lo int phy_cpu_id = cpu_logical_map(smp_processor_id()); 129d457ef35SJoseph Lo u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 130d457ef35SJoseph Lo 131d457ef35SJoseph Lo spin_lock(&tegra_lp2_lock); 132d457ef35SJoseph Lo 133d457ef35SJoseph Lo BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); 134d457ef35SJoseph Lo *cpu_in_lp2 |= BIT(phy_cpu_id); 135d457ef35SJoseph Lo 136d457ef35SJoseph Lo spin_unlock(&tegra_lp2_lock); 137d457ef35SJoseph Lo } 138d552920aSJoseph Lo 139d552920aSJoseph Lo static int tegra_sleep_cpu(unsigned long v2p) 140d552920aSJoseph Lo { 14178ee399fSDmitry Osipenko /* 14278ee399fSDmitry Osipenko * L2 cache disabling using kernel API only allowed when all 14378ee399fSDmitry Osipenko * secondary CPU's are offline. Cache have to be disabled with 14478ee399fSDmitry Osipenko * MMU-on if cache maintenance is done via Trusted Foundations 14578ee399fSDmitry Osipenko * firmware. Note that CPUIDLE won't ever enter powergate on Tegra30 14678ee399fSDmitry Osipenko * if any of secondary CPU's is online and this is the LP2-idle 14778ee399fSDmitry Osipenko * code-path only for Tegra20/30. 14878ee399fSDmitry Osipenko */ 14978ee399fSDmitry Osipenko if (trusted_foundations_registered()) 15078ee399fSDmitry Osipenko outer_disable(); 15178ee399fSDmitry Osipenko 15278ee399fSDmitry Osipenko /* 15378ee399fSDmitry Osipenko * Note that besides of setting up CPU reset vector this firmware 15478ee399fSDmitry Osipenko * call may also do the following, depending on the FW version: 15578ee399fSDmitry Osipenko * 1) Disable L2. But this doesn't matter since we already 15678ee399fSDmitry Osipenko * disabled the L2. 15778ee399fSDmitry Osipenko * 2) Disable D-cache. This need to be taken into account in 15878ee399fSDmitry Osipenko * particular by the tegra_disable_clean_inv_dcache() which 15978ee399fSDmitry Osipenko * shall avoid the re-disable. 16078ee399fSDmitry Osipenko */ 16178ee399fSDmitry Osipenko call_firmware_op(prepare_idle, TF_PM_MODE_LP2); 16278ee399fSDmitry Osipenko 1636affb482SWill Deacon setup_mm_for_reboot(); 164d552920aSJoseph Lo tegra_sleep_cpu_finish(v2p); 165d552920aSJoseph Lo 166d552920aSJoseph Lo /* should never here */ 167d552920aSJoseph Lo BUG(); 168d552920aSJoseph Lo 169d552920aSJoseph Lo return 0; 170d552920aSJoseph Lo } 171d552920aSJoseph Lo 1727232398aSThierry Reding static void tegra_pm_set(enum tegra_suspend_mode mode) 1737232398aSThierry Reding { 1747232398aSThierry Reding u32 value; 1757232398aSThierry Reding 1767232398aSThierry Reding switch (tegra_get_chip_id()) { 1777232398aSThierry Reding case TEGRA20: 1787232398aSThierry Reding case TEGRA30: 1797232398aSThierry Reding break; 1807232398aSThierry Reding default: 1817232398aSThierry Reding /* Turn off CRAIL */ 1827232398aSThierry Reding value = flowctrl_read_cpu_csr(0); 1837232398aSThierry Reding value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK; 1847232398aSThierry Reding value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL; 1857232398aSThierry Reding flowctrl_write_cpu_csr(0, value); 1867232398aSThierry Reding break; 1877232398aSThierry Reding } 1887232398aSThierry Reding 1897232398aSThierry Reding tegra_pmc_enter_suspend_mode(mode); 1907232398aSThierry Reding } 1917232398aSThierry Reding 192*1f3e18ecSDmitry Osipenko int tegra_pm_enter_lp2(void) 193d552920aSJoseph Lo { 194891e1286SDmitry Osipenko int err; 195891e1286SDmitry Osipenko 1967232398aSThierry Reding tegra_pm_set(TEGRA_SUSPEND_LP2); 197d552920aSJoseph Lo 198d552920aSJoseph Lo cpu_cluster_pm_enter(); 199d552920aSJoseph Lo suspend_cpu_complex(); 200d552920aSJoseph Lo 201891e1286SDmitry Osipenko err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 202d552920aSJoseph Lo 20378ee399fSDmitry Osipenko /* 20478ee399fSDmitry Osipenko * Resume L2 cache if it wasn't re-enabled early during resume, 20578ee399fSDmitry Osipenko * which is the case for Tegra30 that has to re-enable the cache 20678ee399fSDmitry Osipenko * via firmware call. In other cases cache is already enabled and 20778ee399fSDmitry Osipenko * hence re-enabling is a no-op. This is always a no-op on Tegra114+. 20878ee399fSDmitry Osipenko */ 20978ee399fSDmitry Osipenko outer_resume(); 21078ee399fSDmitry Osipenko 211d552920aSJoseph Lo restore_cpu_complex(); 212d552920aSJoseph Lo cpu_cluster_pm_exit(); 213891e1286SDmitry Osipenko 214891e1286SDmitry Osipenko return err; 215d552920aSJoseph Lo } 216c8c2e606SJoseph Lo 217c8c2e606SJoseph Lo enum tegra_suspend_mode tegra_pm_validate_suspend_mode( 218c8c2e606SJoseph Lo enum tegra_suspend_mode mode) 219c8c2e606SJoseph Lo { 220c8c2e606SJoseph Lo /* 22195872f42SJoseph Lo * The Tegra devices support suspending to LP1 or lower currently. 222c8c2e606SJoseph Lo */ 22395872f42SJoseph Lo if (mode > TEGRA_SUSPEND_LP1) 22495872f42SJoseph Lo return TEGRA_SUSPEND_LP1; 225c8c2e606SJoseph Lo 226c8c2e606SJoseph Lo return mode; 227c8c2e606SJoseph Lo } 228c8c2e606SJoseph Lo 22995872f42SJoseph Lo static int tegra_sleep_core(unsigned long v2p) 23095872f42SJoseph Lo { 23178ee399fSDmitry Osipenko /* 23278ee399fSDmitry Osipenko * Cache have to be disabled with MMU-on if cache maintenance is done 23378ee399fSDmitry Osipenko * via Trusted Foundations firmware. This is a no-op on Tegra114+. 23478ee399fSDmitry Osipenko */ 23578ee399fSDmitry Osipenko if (trusted_foundations_registered()) 23678ee399fSDmitry Osipenko outer_disable(); 23778ee399fSDmitry Osipenko 23878ee399fSDmitry Osipenko call_firmware_op(prepare_idle, TF_PM_MODE_LP1); 23978ee399fSDmitry Osipenko 24095872f42SJoseph Lo setup_mm_for_reboot(); 24195872f42SJoseph Lo tegra_sleep_core_finish(v2p); 24295872f42SJoseph Lo 24395872f42SJoseph Lo /* should never here */ 24495872f42SJoseph Lo BUG(); 24595872f42SJoseph Lo 24695872f42SJoseph Lo return 0; 24795872f42SJoseph Lo } 24895872f42SJoseph Lo 24995872f42SJoseph Lo /* 25095872f42SJoseph Lo * tegra_lp1_iram_hook 25195872f42SJoseph Lo * 25295872f42SJoseph Lo * Hooking the address of LP1 reset vector and SDRAM self-refresh code in 25395872f42SJoseph Lo * SDRAM. These codes not be copied to IRAM in this fuction. We need to 25495872f42SJoseph Lo * copy these code to IRAM before LP0/LP1 suspend and restore the content 25595872f42SJoseph Lo * of IRAM after resume. 25695872f42SJoseph Lo */ 25795872f42SJoseph Lo static bool tegra_lp1_iram_hook(void) 25895872f42SJoseph Lo { 259304664eaSThierry Reding switch (tegra_get_chip_id()) { 260731a9274SJoseph Lo case TEGRA20: 261731a9274SJoseph Lo if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 262731a9274SJoseph Lo tegra20_lp1_iram_hook(); 263731a9274SJoseph Lo break; 264e7a932b1SJoseph Lo case TEGRA30: 265e9f62449SJoseph Lo case TEGRA114: 266f0c4ac13SJoseph Lo case TEGRA124: 267e9f62449SJoseph Lo if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 268f0c4ac13SJoseph Lo IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 269f0c4ac13SJoseph Lo IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 270e7a932b1SJoseph Lo tegra30_lp1_iram_hook(); 271e7a932b1SJoseph Lo break; 272e7a932b1SJoseph Lo default: 273e7a932b1SJoseph Lo break; 274e7a932b1SJoseph Lo } 275e7a932b1SJoseph Lo 27695872f42SJoseph Lo if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr) 27795872f42SJoseph Lo return false; 27895872f42SJoseph Lo 27995872f42SJoseph Lo iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr; 28095872f42SJoseph Lo iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL); 28195872f42SJoseph Lo if (!iram_save_addr) 28295872f42SJoseph Lo return false; 28395872f42SJoseph Lo 28495872f42SJoseph Lo return true; 28595872f42SJoseph Lo } 28695872f42SJoseph Lo 28795872f42SJoseph Lo static bool tegra_sleep_core_init(void) 28895872f42SJoseph Lo { 289304664eaSThierry Reding switch (tegra_get_chip_id()) { 290731a9274SJoseph Lo case TEGRA20: 291731a9274SJoseph Lo if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 292731a9274SJoseph Lo tegra20_sleep_core_init(); 293731a9274SJoseph Lo break; 294e7a932b1SJoseph Lo case TEGRA30: 295e9f62449SJoseph Lo case TEGRA114: 296f0c4ac13SJoseph Lo case TEGRA124: 297e9f62449SJoseph Lo if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 298f0c4ac13SJoseph Lo IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 299f0c4ac13SJoseph Lo IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 300e7a932b1SJoseph Lo tegra30_sleep_core_init(); 301e7a932b1SJoseph Lo break; 302e7a932b1SJoseph Lo default: 303e7a932b1SJoseph Lo break; 304e7a932b1SJoseph Lo } 305e7a932b1SJoseph Lo 30695872f42SJoseph Lo if (!tegra_sleep_core_finish) 30795872f42SJoseph Lo return false; 30895872f42SJoseph Lo 30995872f42SJoseph Lo return true; 31095872f42SJoseph Lo } 31195872f42SJoseph Lo 31295872f42SJoseph Lo static void tegra_suspend_enter_lp1(void) 31395872f42SJoseph Lo { 31495872f42SJoseph Lo /* copy the reset vector & SDRAM shutdown code into IRAM */ 315fddb770dSStephen Warren memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), 31695872f42SJoseph Lo iram_save_size); 317fddb770dSStephen Warren memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), 318fddb770dSStephen Warren tegra_lp1_iram.start_addr, iram_save_size); 31995872f42SJoseph Lo 32095872f42SJoseph Lo *((u32 *)tegra_cpu_lp1_mask) = 1; 32195872f42SJoseph Lo } 32295872f42SJoseph Lo 32395872f42SJoseph Lo static void tegra_suspend_exit_lp1(void) 32495872f42SJoseph Lo { 32595872f42SJoseph Lo /* restore IRAM */ 326fddb770dSStephen Warren memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, 32795872f42SJoseph Lo iram_save_size); 32895872f42SJoseph Lo 32995872f42SJoseph Lo *(u32 *)tegra_cpu_lp1_mask = 0; 33095872f42SJoseph Lo } 33195872f42SJoseph Lo 332c8c2e606SJoseph Lo static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { 333c8c2e606SJoseph Lo [TEGRA_SUSPEND_NONE] = "none", 334c8c2e606SJoseph Lo [TEGRA_SUSPEND_LP2] = "LP2", 335c8c2e606SJoseph Lo [TEGRA_SUSPEND_LP1] = "LP1", 336c8c2e606SJoseph Lo [TEGRA_SUSPEND_LP0] = "LP0", 337c8c2e606SJoseph Lo }; 338c8c2e606SJoseph Lo 3398bd26e3aSPaul Gortmaker static int tegra_suspend_enter(suspend_state_t state) 340c8c2e606SJoseph Lo { 341c8c2e606SJoseph Lo enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); 342c8c2e606SJoseph Lo 343c8c2e606SJoseph Lo if (WARN_ON(mode < TEGRA_SUSPEND_NONE || 344c8c2e606SJoseph Lo mode >= TEGRA_MAX_SUSPEND_MODE)) 345c8c2e606SJoseph Lo return -EINVAL; 346c8c2e606SJoseph Lo 347c8c2e606SJoseph Lo pr_info("Entering suspend state %s\n", lp_state[mode]); 348c8c2e606SJoseph Lo 3497232398aSThierry Reding tegra_pm_set(mode); 350c8c2e606SJoseph Lo 351c8c2e606SJoseph Lo local_fiq_disable(); 352c8c2e606SJoseph Lo 353c8c2e606SJoseph Lo suspend_cpu_complex(); 354c8c2e606SJoseph Lo switch (mode) { 35595872f42SJoseph Lo case TEGRA_SUSPEND_LP1: 35695872f42SJoseph Lo tegra_suspend_enter_lp1(); 35795872f42SJoseph Lo break; 358c8c2e606SJoseph Lo case TEGRA_SUSPEND_LP2: 359*1f3e18ecSDmitry Osipenko tegra_pm_set_cpu_in_lp2(); 360c8c2e606SJoseph Lo break; 361c8c2e606SJoseph Lo default: 362c8c2e606SJoseph Lo break; 363c8c2e606SJoseph Lo } 364c8c2e606SJoseph Lo 36595872f42SJoseph Lo cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func); 366c8c2e606SJoseph Lo 36778ee399fSDmitry Osipenko /* 36878ee399fSDmitry Osipenko * Resume L2 cache if it wasn't re-enabled early during resume, 36978ee399fSDmitry Osipenko * which is the case for Tegra30 that has to re-enable the cache 37078ee399fSDmitry Osipenko * via firmware call. In other cases cache is already enabled and 37178ee399fSDmitry Osipenko * hence re-enabling is a no-op. 37278ee399fSDmitry Osipenko */ 37378ee399fSDmitry Osipenko outer_resume(); 37478ee399fSDmitry Osipenko 375c8c2e606SJoseph Lo switch (mode) { 37695872f42SJoseph Lo case TEGRA_SUSPEND_LP1: 37795872f42SJoseph Lo tegra_suspend_exit_lp1(); 37895872f42SJoseph Lo break; 379c8c2e606SJoseph Lo case TEGRA_SUSPEND_LP2: 380*1f3e18ecSDmitry Osipenko tegra_pm_clear_cpu_in_lp2(); 381c8c2e606SJoseph Lo break; 382c8c2e606SJoseph Lo default: 383c8c2e606SJoseph Lo break; 384c8c2e606SJoseph Lo } 385c8c2e606SJoseph Lo restore_cpu_complex(); 386c8c2e606SJoseph Lo 387c8c2e606SJoseph Lo local_fiq_enable(); 388c8c2e606SJoseph Lo 389c8c2e606SJoseph Lo return 0; 390c8c2e606SJoseph Lo } 391c8c2e606SJoseph Lo 392c8c2e606SJoseph Lo static const struct platform_suspend_ops tegra_suspend_ops = { 393c8c2e606SJoseph Lo .valid = suspend_valid_only_mem, 394c8c2e606SJoseph Lo .enter = tegra_suspend_enter, 395c8c2e606SJoseph Lo }; 396c8c2e606SJoseph Lo 397c8c2e606SJoseph Lo void __init tegra_init_suspend(void) 398c8c2e606SJoseph Lo { 39995872f42SJoseph Lo enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); 40095872f42SJoseph Lo 40195872f42SJoseph Lo if (mode == TEGRA_SUSPEND_NONE) 402c8c2e606SJoseph Lo return; 403c8c2e606SJoseph Lo 404bf91add4SJoseph Lo tegra_tear_down_cpu_init(); 405c8c2e606SJoseph Lo 40695872f42SJoseph Lo if (mode >= TEGRA_SUSPEND_LP1) { 40795872f42SJoseph Lo if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { 40895872f42SJoseph Lo pr_err("%s: unable to allocate memory for SDRAM" 40995872f42SJoseph Lo "self-refresh -- LP0/LP1 unavailable\n", 41095872f42SJoseph Lo __func__); 41195872f42SJoseph Lo tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2); 41295872f42SJoseph Lo mode = TEGRA_SUSPEND_LP2; 41395872f42SJoseph Lo } 41495872f42SJoseph Lo } 41595872f42SJoseph Lo 41695872f42SJoseph Lo /* set up sleep function for cpu_suspend */ 41795872f42SJoseph Lo switch (mode) { 41895872f42SJoseph Lo case TEGRA_SUSPEND_LP1: 41995872f42SJoseph Lo tegra_sleep_func = tegra_sleep_core; 42095872f42SJoseph Lo break; 42195872f42SJoseph Lo case TEGRA_SUSPEND_LP2: 42295872f42SJoseph Lo tegra_sleep_func = tegra_sleep_cpu; 42395872f42SJoseph Lo break; 42495872f42SJoseph Lo default: 42595872f42SJoseph Lo break; 42695872f42SJoseph Lo } 42795872f42SJoseph Lo 428c8c2e606SJoseph Lo suspend_set_ops(&tegra_suspend_ops); 429c8c2e606SJoseph Lo } 430859a6f6eSDmitry Osipenko 431859a6f6eSDmitry Osipenko int tegra_pm_park_secondary_cpu(unsigned long cpu) 432859a6f6eSDmitry Osipenko { 433859a6f6eSDmitry Osipenko if (cpu > 0) { 434859a6f6eSDmitry Osipenko tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); 435859a6f6eSDmitry Osipenko 436859a6f6eSDmitry Osipenko if (tegra_get_chip_id() == TEGRA20) 437859a6f6eSDmitry Osipenko tegra20_hotplug_shutdown(); 438859a6f6eSDmitry Osipenko else 439859a6f6eSDmitry Osipenko tegra30_hotplug_shutdown(); 440859a6f6eSDmitry Osipenko } 441859a6f6eSDmitry Osipenko 442859a6f6eSDmitry Osipenko return -EINVAL; 443859a6f6eSDmitry Osipenko } 444d457ef35SJoseph Lo #endif 445