1*9c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 25ad36c5fSErik Gilling /* 3938fa349SColin Cross * Copyright (C) 2011 Google, Inc. 45ad36c5fSErik Gilling * 55ad36c5fSErik Gilling * Author: 6938fa349SColin Cross * Colin Cross <ccross@android.com> 75ad36c5fSErik Gilling * 8e307cc89SJoseph Lo * Copyright (C) 2010,2013, NVIDIA Corporation 95ad36c5fSErik Gilling */ 105ad36c5fSErik Gilling 117e8b15dbSJoseph Lo #include <linux/cpu_pm.h> 125ad36c5fSErik Gilling #include <linux/interrupt.h> 135ad36c5fSErik Gilling #include <linux/io.h> 14520f7bd7SRob Herring #include <linux/irqchip/arm-gic.h> 15a0524accSThierry Reding #include <linux/irq.h> 16a0524accSThierry Reding #include <linux/kernel.h> 17a0524accSThierry Reding #include <linux/of_address.h> 18a0524accSThierry Reding #include <linux/of.h> 19e307cc89SJoseph Lo #include <linux/syscore_ops.h> 205ad36c5fSErik Gilling 215ad36c5fSErik Gilling #include "board.h" 222be39c07SStephen Warren #include "iomap.h" 234f71a888SThierry Reding #include "irq.h" 245ad36c5fSErik Gilling 25d4b92fb2SJoseph Lo #define SGI_MASK 0xFFFF 26d4b92fb2SJoseph Lo 27e307cc89SJoseph Lo #ifdef CONFIG_PM_SLEEP 287e8b15dbSJoseph Lo static void __iomem *tegra_gic_cpu_base; 29e307cc89SJoseph Lo #endif 30e307cc89SJoseph Lo 31d4b92fb2SJoseph Lo bool tegra_pending_sgi(void) 32d4b92fb2SJoseph Lo { 33d4b92fb2SJoseph Lo u32 pending_set; 34d4b92fb2SJoseph Lo void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); 35d4b92fb2SJoseph Lo 36d4b92fb2SJoseph Lo pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET); 37d4b92fb2SJoseph Lo 38d4b92fb2SJoseph Lo if (pending_set & SGI_MASK) 39d4b92fb2SJoseph Lo return true; 40d4b92fb2SJoseph Lo 41d4b92fb2SJoseph Lo return false; 42d4b92fb2SJoseph Lo } 43d4b92fb2SJoseph Lo 44e307cc89SJoseph Lo #ifdef CONFIG_PM_SLEEP 457e8b15dbSJoseph Lo static int tegra_gic_notifier(struct notifier_block *self, 467e8b15dbSJoseph Lo unsigned long cmd, void *v) 477e8b15dbSJoseph Lo { 487e8b15dbSJoseph Lo switch (cmd) { 497e8b15dbSJoseph Lo case CPU_PM_ENTER: 507e8b15dbSJoseph Lo writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); 517e8b15dbSJoseph Lo break; 527e8b15dbSJoseph Lo } 537e8b15dbSJoseph Lo 547e8b15dbSJoseph Lo return NOTIFY_OK; 557e8b15dbSJoseph Lo } 567e8b15dbSJoseph Lo 577e8b15dbSJoseph Lo static struct notifier_block tegra_gic_notifier_block = { 587e8b15dbSJoseph Lo .notifier_call = tegra_gic_notifier, 597e8b15dbSJoseph Lo }; 607e8b15dbSJoseph Lo 617e8b15dbSJoseph Lo static const struct of_device_id tegra114_dt_gic_match[] __initconst = { 627e8b15dbSJoseph Lo { .compatible = "arm,cortex-a15-gic" }, 637e8b15dbSJoseph Lo { } 647e8b15dbSJoseph Lo }; 657e8b15dbSJoseph Lo 664dd201beSArnd Bergmann static void __init tegra114_gic_cpu_pm_registration(void) 677e8b15dbSJoseph Lo { 687e8b15dbSJoseph Lo struct device_node *dn; 697e8b15dbSJoseph Lo 707e8b15dbSJoseph Lo dn = of_find_matching_node(NULL, tegra114_dt_gic_match); 717e8b15dbSJoseph Lo if (!dn) 727e8b15dbSJoseph Lo return; 737e8b15dbSJoseph Lo 747e8b15dbSJoseph Lo tegra_gic_cpu_base = of_iomap(dn, 1); 757e8b15dbSJoseph Lo 767e8b15dbSJoseph Lo cpu_pm_register_notifier(&tegra_gic_notifier_block); 777e8b15dbSJoseph Lo } 78e307cc89SJoseph Lo #else 794dd201beSArnd Bergmann static void __init tegra114_gic_cpu_pm_registration(void) { } 80e307cc89SJoseph Lo #endif 81e307cc89SJoseph Lo 82e9479e0eSMarc Zyngier static const struct of_device_id tegra_ictlr_match[] __initconst = { 83e9479e0eSMarc Zyngier { .compatible = "nvidia,tegra20-ictlr" }, 84e9479e0eSMarc Zyngier { .compatible = "nvidia,tegra30-ictlr" }, 85e9479e0eSMarc Zyngier { } 86e9479e0eSMarc Zyngier }; 87e9479e0eSMarc Zyngier 885ad36c5fSErik Gilling void __init tegra_init_irq(void) 895ad36c5fSErik Gilling { 901a703bffSMarc Zyngier if (WARN_ON(!of_find_matching_node(NULL, tegra_ictlr_match))) 911a703bffSMarc Zyngier pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 92d1d8c666SColin Cross 937e8b15dbSJoseph Lo tegra114_gic_cpu_pm_registration(); 94460907bcSGary King } 95