1*dff052ccSMylène Josserand/* SPDX-License-Identifier: GPL-2.0 2*dff052ccSMylène Josserand * 3*dff052ccSMylène Josserand * Copyright (c) 2018 Chen-Yu Tsai 4*dff052ccSMylène Josserand * Copyright (c) 2018 Bootlin 5*dff052ccSMylène Josserand * 6*dff052ccSMylène Josserand * Chen-Yu Tsai <wens@csie.org> 7*dff052ccSMylène Josserand * Mylène Josserand <mylene.josserand@bootlin.com> 8*dff052ccSMylène Josserand * 9*dff052ccSMylène Josserand * SMP support for sunxi based systems with Cortex A7/A15 10*dff052ccSMylène Josserand * 11*dff052ccSMylène Josserand */ 12*dff052ccSMylène Josserand 13*dff052ccSMylène Josserand#include <linux/linkage.h> 14*dff052ccSMylène Josserand#include <asm/assembler.h> 15*dff052ccSMylène Josserand#include <asm/cputype.h> 16*dff052ccSMylène Josserand 17*dff052ccSMylène JosserandENTRY(sunxi_mc_smp_cluster_cache_enable) 18*dff052ccSMylène Josserand .arch armv7-a 19*dff052ccSMylène Josserand /* 20*dff052ccSMylène Josserand * Enable cluster-level coherency, in preparation for turning on the MMU. 21*dff052ccSMylène Josserand * 22*dff052ccSMylène Josserand * Also enable regional clock gating and L2 data latency settings for 23*dff052ccSMylène Josserand * Cortex-A15. These settings are from the vendor kernel. 24*dff052ccSMylène Josserand */ 25*dff052ccSMylène Josserand mrc p15, 0, r1, c0, c0, 0 26*dff052ccSMylène Josserand movw r2, #(ARM_CPU_PART_MASK & 0xffff) 27*dff052ccSMylène Josserand movt r2, #(ARM_CPU_PART_MASK >> 16) 28*dff052ccSMylène Josserand and r1, r1, r2 29*dff052ccSMylène Josserand movw r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff) 30*dff052ccSMylène Josserand movt r2, #(ARM_CPU_PART_CORTEX_A15 >> 16) 31*dff052ccSMylène Josserand cmp r1, r2 32*dff052ccSMylène Josserand bne not_a15 33*dff052ccSMylène Josserand 34*dff052ccSMylène Josserand /* The following is Cortex-A15 specific */ 35*dff052ccSMylène Josserand 36*dff052ccSMylène Josserand /* ACTLR2: Enable CPU regional clock gates */ 37*dff052ccSMylène Josserand mrc p15, 1, r1, c15, c0, 4 38*dff052ccSMylène Josserand orr r1, r1, #(0x1 << 31) 39*dff052ccSMylène Josserand mcr p15, 1, r1, c15, c0, 4 40*dff052ccSMylène Josserand 41*dff052ccSMylène Josserand /* L2ACTLR */ 42*dff052ccSMylène Josserand mrc p15, 1, r1, c15, c0, 0 43*dff052ccSMylène Josserand /* Enable L2, GIC, and Timer regional clock gates */ 44*dff052ccSMylène Josserand orr r1, r1, #(0x1 << 26) 45*dff052ccSMylène Josserand /* Disable clean/evict from being pushed to external */ 46*dff052ccSMylène Josserand orr r1, r1, #(0x1<<3) 47*dff052ccSMylène Josserand mcr p15, 1, r1, c15, c0, 0 48*dff052ccSMylène Josserand 49*dff052ccSMylène Josserand /* L2CTRL: L2 data RAM latency */ 50*dff052ccSMylène Josserand mrc p15, 1, r1, c9, c0, 2 51*dff052ccSMylène Josserand bic r1, r1, #(0x7 << 0) 52*dff052ccSMylène Josserand orr r1, r1, #(0x3 << 0) 53*dff052ccSMylène Josserand mcr p15, 1, r1, c9, c0, 2 54*dff052ccSMylène Josserand 55*dff052ccSMylène Josserand /* End of Cortex-A15 specific setup */ 56*dff052ccSMylène Josserand not_a15: 57*dff052ccSMylène Josserand 58*dff052ccSMylène Josserand /* Get value of sunxi_mc_smp_first_comer */ 59*dff052ccSMylène Josserand adr r1, first 60*dff052ccSMylène Josserand ldr r0, [r1] 61*dff052ccSMylène Josserand ldr r0, [r1, r0] 62*dff052ccSMylène Josserand 63*dff052ccSMylène Josserand /* Skip cci_enable_port_for_self if not first comer */ 64*dff052ccSMylène Josserand cmp r0, #0 65*dff052ccSMylène Josserand bxeq lr 66*dff052ccSMylène Josserand b cci_enable_port_for_self 67*dff052ccSMylène Josserand 68*dff052ccSMylène Josserand .align 2 69*dff052ccSMylène Josserand first: .word sunxi_mc_smp_first_comer - . 70*dff052ccSMylène JosserandENDPROC(sunxi_mc_smp_cluster_cache_enable) 71*dff052ccSMylène Josserand 72*dff052ccSMylène JosserandENTRY(sunxi_mc_smp_secondary_startup) 73*dff052ccSMylène Josserand bl sunxi_mc_smp_cluster_cache_enable 74*dff052ccSMylène Josserand b secondary_startup 75*dff052ccSMylène JosserandENDPROC(sunxi_mc_smp_secondary_startup) 76*dff052ccSMylène Josserand 77*dff052ccSMylène JosserandENTRY(sunxi_mc_smp_resume) 78*dff052ccSMylène Josserand bl sunxi_mc_smp_cluster_cache_enable 79*dff052ccSMylène Josserand b cpu_resume 80*dff052ccSMylène JosserandENDPROC(sunxi_mc_smp_resume) 81