1 /* 2 * r8a73a4 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Magnus Damm 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 #include <linux/irq.h> 17 #include <linux/kernel.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_data/irq-renesas-irqc.h> 20 #include <linux/serial_sci.h> 21 #include <linux/sh_dma.h> 22 #include <linux/sh_timer.h> 23 24 #include <asm/mach/arch.h> 25 26 #include "common.h" 27 #include "dma-register.h" 28 #include "irqs.h" 29 #include "r8a73a4.h" 30 31 static const struct resource pfc_resources[] = { 32 DEFINE_RES_MEM(0xe6050000, 0x9000), 33 }; 34 35 void __init r8a73a4_pinmux_init(void) 36 { 37 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources, 38 ARRAY_SIZE(pfc_resources)); 39 } 40 41 #define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \ 42 static struct plat_sci_port scif##index##_platform_data = { \ 43 .type = scif_type, \ 44 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 45 .scscr = _scscr, \ 46 }; \ 47 \ 48 static struct resource scif##index##_resources[] = { \ 49 DEFINE_RES_MEM(baseaddr, 0x100), \ 50 DEFINE_RES_IRQ(irq), \ 51 } 52 53 #define R8A73A4_SCIFA(index, baseaddr, irq) \ 54 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ 55 index, baseaddr, irq) 56 57 #define R8A73A4_SCIFB(index, baseaddr, irq) \ 58 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ 59 index, baseaddr, irq) 60 61 R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ 62 R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ 63 R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ 64 R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ 65 R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ 66 R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */ 67 68 #define r8a73a4_register_scif(index) \ 69 platform_device_register_resndata(NULL, "sh-sci", index, \ 70 scif##index##_resources, \ 71 ARRAY_SIZE(scif##index##_resources), \ 72 &scif##index##_platform_data, \ 73 sizeof(scif##index##_platform_data)) 74 75 static const struct renesas_irqc_config irqc0_data = { 76 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ 77 }; 78 79 static const struct resource irqc0_resources[] = { 80 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ 81 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ 82 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ 83 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ 84 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ 85 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ 86 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ 87 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ 88 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ 89 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ 90 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ 91 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ 92 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ 93 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ 94 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ 95 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ 96 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */ 97 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */ 98 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */ 99 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */ 100 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */ 101 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */ 102 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */ 103 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */ 104 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */ 105 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */ 106 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */ 107 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */ 108 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */ 109 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */ 110 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */ 111 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */ 112 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */ 113 }; 114 115 static const struct renesas_irqc_config irqc1_data = { 116 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */ 117 }; 118 119 static const struct resource irqc1_resources[] = { 120 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */ 121 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */ 122 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */ 123 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */ 124 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */ 125 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */ 126 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */ 127 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */ 128 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */ 129 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */ 130 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */ 131 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */ 132 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */ 133 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */ 134 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */ 135 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */ 136 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */ 137 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */ 138 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */ 139 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */ 140 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */ 141 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */ 142 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */ 143 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */ 144 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */ 145 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */ 146 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */ 147 }; 148 149 #define r8a73a4_register_irqc(idx) \ 150 platform_device_register_resndata(NULL, "renesas_irqc", \ 151 idx, irqc##idx##_resources, \ 152 ARRAY_SIZE(irqc##idx##_resources), \ 153 &irqc##idx##_data, \ 154 sizeof(struct renesas_irqc_config)) 155 156 /* Thermal0 -> Thermal2 */ 157 static const struct resource thermal0_resources[] = { 158 DEFINE_RES_MEM(0xe61f0000, 0x14), 159 DEFINE_RES_MEM(0xe61f0100, 0x38), 160 DEFINE_RES_MEM(0xe61f0200, 0x38), 161 DEFINE_RES_MEM(0xe61f0300, 0x38), 162 DEFINE_RES_IRQ(gic_spi(69)), 163 }; 164 165 #define r8a73a4_register_thermal() \ 166 platform_device_register_simple("rcar_thermal", -1, \ 167 thermal0_resources, \ 168 ARRAY_SIZE(thermal0_resources)) 169 170 static struct sh_timer_config cmt1_platform_data = { 171 .channels_mask = 0xff, 172 }; 173 174 static struct resource cmt1_resources[] = { 175 DEFINE_RES_MEM(0xe6130000, 0x1004), 176 DEFINE_RES_IRQ(gic_spi(120)), 177 }; 178 179 #define r8a73a4_register_cmt(idx) \ 180 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \ 181 idx, cmt##idx##_resources, \ 182 ARRAY_SIZE(cmt##idx##_resources), \ 183 &cmt##idx##_platform_data, \ 184 sizeof(struct sh_timer_config)) 185 186 /* DMA */ 187 static const struct sh_dmae_slave_config dma_slaves[] = { 188 { 189 .slave_id = SHDMA_SLAVE_MMCIF0_TX, 190 .addr = 0xee200034, 191 .chcr = CHCR_TX(XMIT_SZ_32BIT), 192 .mid_rid = 0xd1, 193 }, { 194 .slave_id = SHDMA_SLAVE_MMCIF0_RX, 195 .addr = 0xee200034, 196 .chcr = CHCR_RX(XMIT_SZ_32BIT), 197 .mid_rid = 0xd2, 198 }, { 199 .slave_id = SHDMA_SLAVE_MMCIF1_TX, 200 .addr = 0xee220034, 201 .chcr = CHCR_TX(XMIT_SZ_32BIT), 202 .mid_rid = 0xe1, 203 }, { 204 .slave_id = SHDMA_SLAVE_MMCIF1_RX, 205 .addr = 0xee220034, 206 .chcr = CHCR_RX(XMIT_SZ_32BIT), 207 .mid_rid = 0xe2, 208 }, 209 }; 210 211 #define DMAE_CHANNEL(a, b) \ 212 { \ 213 .offset = (a) - 0x20, \ 214 .dmars = (a) - 0x20 + 0x40, \ 215 .chclr_bit = (b), \ 216 .chclr_offset = 0x80 - 0x20, \ 217 } 218 219 static const struct sh_dmae_channel dma_channels[] = { 220 DMAE_CHANNEL(0x8000, 0), 221 DMAE_CHANNEL(0x8080, 1), 222 DMAE_CHANNEL(0x8100, 2), 223 DMAE_CHANNEL(0x8180, 3), 224 DMAE_CHANNEL(0x8200, 4), 225 DMAE_CHANNEL(0x8280, 5), 226 DMAE_CHANNEL(0x8300, 6), 227 DMAE_CHANNEL(0x8380, 7), 228 DMAE_CHANNEL(0x8400, 8), 229 DMAE_CHANNEL(0x8480, 9), 230 DMAE_CHANNEL(0x8500, 10), 231 DMAE_CHANNEL(0x8580, 11), 232 DMAE_CHANNEL(0x8600, 12), 233 DMAE_CHANNEL(0x8680, 13), 234 DMAE_CHANNEL(0x8700, 14), 235 DMAE_CHANNEL(0x8780, 15), 236 DMAE_CHANNEL(0x8800, 16), 237 DMAE_CHANNEL(0x8880, 17), 238 DMAE_CHANNEL(0x8900, 18), 239 DMAE_CHANNEL(0x8980, 19), 240 }; 241 242 static const struct sh_dmae_pdata dma_pdata = { 243 .slave = dma_slaves, 244 .slave_num = ARRAY_SIZE(dma_slaves), 245 .channel = dma_channels, 246 .channel_num = ARRAY_SIZE(dma_channels), 247 .ts_low_shift = TS_LOW_SHIFT, 248 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 249 .ts_high_shift = TS_HI_SHIFT, 250 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 251 .ts_shift = dma_ts_shift, 252 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 253 .dmaor_init = DMAOR_DME, 254 .chclr_present = 1, 255 .chclr_bitwise = 1, 256 }; 257 258 static struct resource dma_resources[] = { 259 DEFINE_RES_MEM(0xe6700020, 0x89e0), 260 DEFINE_RES_IRQ(gic_spi(220)), 261 { 262 /* IRQ for channels 0-19 */ 263 .start = gic_spi(200), 264 .end = gic_spi(219), 265 .flags = IORESOURCE_IRQ, 266 }, 267 }; 268 269 #define r8a73a4_register_dmac() \ 270 platform_device_register_resndata(NULL, "sh-dma-engine", 0, \ 271 dma_resources, ARRAY_SIZE(dma_resources), \ 272 &dma_pdata, sizeof(dma_pdata)) 273 274 void __init r8a73a4_add_standard_devices(void) 275 { 276 r8a73a4_register_cmt(1); 277 r8a73a4_register_scif(0); 278 r8a73a4_register_scif(1); 279 r8a73a4_register_scif(2); 280 r8a73a4_register_scif(3); 281 r8a73a4_register_scif(4); 282 r8a73a4_register_scif(5); 283 r8a73a4_register_irqc(0); 284 r8a73a4_register_irqc(1); 285 r8a73a4_register_thermal(); 286 r8a73a4_register_dmac(); 287 } 288 289 #ifdef CONFIG_USE_OF 290 291 static const char *r8a73a4_boards_compat_dt[] __initdata = { 292 "renesas,r8a73a4", 293 NULL, 294 }; 295 296 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") 297 .init_early = shmobile_init_delay, 298 .init_late = shmobile_init_late, 299 .dt_compat = r8a73a4_boards_compat_dt, 300 MACHINE_END 301 #endif /* CONFIG_USE_OF */ 302