1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-sa1100/generic.c 4 * 5 * Author: Nicolas Pitre 6 * 7 * Code common to all SA11x0 machines. 8 */ 9 #include <linux/gpio.h> 10 #include <linux/gpio/machine.h> 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/pm.h> 17 #include <linux/cpufreq.h> 18 #include <linux/ioport.h> 19 #include <linux/platform_device.h> 20 #include <linux/reboot.h> 21 #include <linux/regulator/fixed.h> 22 #include <linux/regulator/machine.h> 23 #include <linux/irqchip/irq-sa11x0.h> 24 25 #include <video/sa1100fb.h> 26 27 #include <soc/sa1100/pwer.h> 28 29 #include <asm/div64.h> 30 #include <asm/mach/map.h> 31 #include <asm/mach/flash.h> 32 #include <asm/irq.h> 33 #include <asm/system_misc.h> 34 35 #include <mach/hardware.h> 36 #include <mach/irqs.h> 37 #include <mach/reset.h> 38 39 #include "generic.h" 40 #include <clocksource/pxa.h> 41 42 #define NR_FREQS 16 43 44 /* 45 * This table is setup for a 3.6864MHz Crystal. 46 */ 47 struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = { 48 { .frequency = 59000, /* 59.0 MHz */}, 49 { .frequency = 73700, /* 73.7 MHz */}, 50 { .frequency = 88500, /* 88.5 MHz */}, 51 { .frequency = 103200, /* 103.2 MHz */}, 52 { .frequency = 118000, /* 118.0 MHz */}, 53 { .frequency = 132700, /* 132.7 MHz */}, 54 { .frequency = 147500, /* 147.5 MHz */}, 55 { .frequency = 162200, /* 162.2 MHz */}, 56 { .frequency = 176900, /* 176.9 MHz */}, 57 { .frequency = 191700, /* 191.7 MHz */}, 58 { .frequency = 206400, /* 206.4 MHz */}, 59 { .frequency = 221200, /* 221.2 MHz */}, 60 { .frequency = 235900, /* 235.9 MHz */}, 61 { .frequency = 250700, /* 250.7 MHz */}, 62 { .frequency = 265400, /* 265.4 MHz */}, 63 { .frequency = 280200, /* 280.2 MHz */}, 64 { .frequency = CPUFREQ_TABLE_END, }, 65 }; 66 67 unsigned int sa11x0_getspeed(unsigned int cpu) 68 { 69 if (cpu) 70 return 0; 71 return sa11x0_freq_table[PPCR & 0xf].frequency; 72 } 73 74 /* 75 * Default power-off for SA1100 76 */ 77 static void sa1100_power_off(void) 78 { 79 mdelay(100); 80 local_irq_disable(); 81 /* disable internal oscillator, float CS lines */ 82 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); 83 /* enable wake-up on GPIO0 (Assabet...) */ 84 PWER = GFER = GRER = 1; 85 /* 86 * set scratchpad to zero, just in case it is used as a 87 * restart address by the bootloader. 88 */ 89 PSPR = 0; 90 /* enter sleep mode */ 91 PMCR = PMCR_SF; 92 } 93 94 void sa11x0_restart(enum reboot_mode mode, const char *cmd) 95 { 96 clear_reset_status(RESET_STATUS_ALL); 97 98 if (mode == REBOOT_SOFT) { 99 /* Jump into ROM at address 0 */ 100 soft_restart(0); 101 } else { 102 /* Use on-chip reset capability */ 103 RSRR = RSRR_SWR; 104 } 105 } 106 107 static void sa11x0_register_device(struct platform_device *dev, void *data) 108 { 109 int err; 110 dev->dev.platform_data = data; 111 err = platform_device_register(dev); 112 if (err) 113 printk(KERN_ERR "Unable to register device %s: %d\n", 114 dev->name, err); 115 } 116 117 118 static struct resource sa11x0udc_resources[] = { 119 [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K), 120 [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC), 121 }; 122 123 static u64 sa11x0udc_dma_mask = 0xffffffffUL; 124 125 static struct platform_device sa11x0udc_device = { 126 .name = "sa11x0-udc", 127 .id = -1, 128 .dev = { 129 .dma_mask = &sa11x0udc_dma_mask, 130 .coherent_dma_mask = 0xffffffff, 131 }, 132 .num_resources = ARRAY_SIZE(sa11x0udc_resources), 133 .resource = sa11x0udc_resources, 134 }; 135 136 static struct resource sa11x0uart1_resources[] = { 137 [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K), 138 [1] = DEFINE_RES_IRQ(IRQ_Ser1UART), 139 }; 140 141 static struct platform_device sa11x0uart1_device = { 142 .name = "sa11x0-uart", 143 .id = 1, 144 .num_resources = ARRAY_SIZE(sa11x0uart1_resources), 145 .resource = sa11x0uart1_resources, 146 }; 147 148 static struct resource sa11x0uart3_resources[] = { 149 [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K), 150 [1] = DEFINE_RES_IRQ(IRQ_Ser3UART), 151 }; 152 153 static struct platform_device sa11x0uart3_device = { 154 .name = "sa11x0-uart", 155 .id = 3, 156 .num_resources = ARRAY_SIZE(sa11x0uart3_resources), 157 .resource = sa11x0uart3_resources, 158 }; 159 160 static struct resource sa11x0mcp_resources[] = { 161 [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K), 162 [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4), 163 [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP), 164 }; 165 166 static u64 sa11x0mcp_dma_mask = 0xffffffffUL; 167 168 static struct platform_device sa11x0mcp_device = { 169 .name = "sa11x0-mcp", 170 .id = -1, 171 .dev = { 172 .dma_mask = &sa11x0mcp_dma_mask, 173 .coherent_dma_mask = 0xffffffff, 174 }, 175 .num_resources = ARRAY_SIZE(sa11x0mcp_resources), 176 .resource = sa11x0mcp_resources, 177 }; 178 179 void __init sa11x0_ppc_configure_mcp(void) 180 { 181 /* Setup the PPC unit for the MCP */ 182 PPDR &= ~PPC_RXD4; 183 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; 184 PSDR |= PPC_RXD4; 185 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); 186 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); 187 } 188 189 void sa11x0_register_mcp(struct mcp_plat_data *data) 190 { 191 sa11x0_register_device(&sa11x0mcp_device, data); 192 } 193 194 static struct resource sa11x0ssp_resources[] = { 195 [0] = DEFINE_RES_MEM(0x80070000, SZ_64K), 196 [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP), 197 }; 198 199 static u64 sa11x0ssp_dma_mask = 0xffffffffUL; 200 201 static struct platform_device sa11x0ssp_device = { 202 .name = "sa11x0-ssp", 203 .id = -1, 204 .dev = { 205 .dma_mask = &sa11x0ssp_dma_mask, 206 .coherent_dma_mask = 0xffffffff, 207 }, 208 .num_resources = ARRAY_SIZE(sa11x0ssp_resources), 209 .resource = sa11x0ssp_resources, 210 }; 211 212 static struct resource sa11x0fb_resources[] = { 213 [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K), 214 [1] = DEFINE_RES_IRQ(IRQ_LCD), 215 }; 216 217 static struct platform_device sa11x0fb_device = { 218 .name = "sa11x0-fb", 219 .id = -1, 220 .dev = { 221 .coherent_dma_mask = 0xffffffff, 222 }, 223 .num_resources = ARRAY_SIZE(sa11x0fb_resources), 224 .resource = sa11x0fb_resources, 225 }; 226 227 void sa11x0_register_lcd(struct sa1100fb_mach_info *inf) 228 { 229 sa11x0_register_device(&sa11x0fb_device, inf); 230 } 231 232 void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *table) 233 { 234 if (table) 235 gpiod_add_lookup_table(table); 236 platform_device_register_simple("sa11x0-pcmcia", socket, NULL, 0); 237 } 238 239 static struct platform_device sa11x0mtd_device = { 240 .name = "sa1100-mtd", 241 .id = -1, 242 }; 243 244 void sa11x0_register_mtd(struct flash_platform_data *flash, 245 struct resource *res, int nr) 246 { 247 flash->name = "sa1100"; 248 sa11x0mtd_device.resource = res; 249 sa11x0mtd_device.num_resources = nr; 250 sa11x0_register_device(&sa11x0mtd_device, flash); 251 } 252 253 static struct resource sa11x0ir_resources[] = { 254 DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24), 255 DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c), 256 DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04), 257 DEFINE_RES_IRQ(IRQ_Ser2ICP), 258 }; 259 260 static struct platform_device sa11x0ir_device = { 261 .name = "sa11x0-ir", 262 .id = -1, 263 .num_resources = ARRAY_SIZE(sa11x0ir_resources), 264 .resource = sa11x0ir_resources, 265 }; 266 267 void sa11x0_register_irda(struct irda_platform_data *irda) 268 { 269 sa11x0_register_device(&sa11x0ir_device, irda); 270 } 271 272 static struct resource sa1100_rtc_resources[] = { 273 DEFINE_RES_MEM(0x90010000, 0x40), 274 DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"), 275 DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"), 276 }; 277 278 static struct platform_device sa11x0rtc_device = { 279 .name = "sa1100-rtc", 280 .id = -1, 281 .num_resources = ARRAY_SIZE(sa1100_rtc_resources), 282 .resource = sa1100_rtc_resources, 283 }; 284 285 static struct resource sa11x0dma_resources[] = { 286 DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE), 287 DEFINE_RES_IRQ(IRQ_DMA0), 288 DEFINE_RES_IRQ(IRQ_DMA1), 289 DEFINE_RES_IRQ(IRQ_DMA2), 290 DEFINE_RES_IRQ(IRQ_DMA3), 291 DEFINE_RES_IRQ(IRQ_DMA4), 292 DEFINE_RES_IRQ(IRQ_DMA5), 293 }; 294 295 static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32); 296 297 static struct platform_device sa11x0dma_device = { 298 .name = "sa11x0-dma", 299 .id = -1, 300 .dev = { 301 .dma_mask = &sa11x0dma_dma_mask, 302 .coherent_dma_mask = 0xffffffff, 303 }, 304 .num_resources = ARRAY_SIZE(sa11x0dma_resources), 305 .resource = sa11x0dma_resources, 306 }; 307 308 static struct platform_device *sa11x0_devices[] __initdata = { 309 &sa11x0udc_device, 310 &sa11x0uart1_device, 311 &sa11x0uart3_device, 312 &sa11x0ssp_device, 313 &sa11x0rtc_device, 314 &sa11x0dma_device, 315 }; 316 317 static int __init sa1100_init(void) 318 { 319 struct resource wdt_res = DEFINE_RES_MEM(0x90000000, 0x20); 320 pm_power_off = sa1100_power_off; 321 322 regulator_has_full_constraints(); 323 324 platform_device_register_simple("sa1100_wdt", -1, &wdt_res, 1); 325 326 return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices)); 327 } 328 329 arch_initcall(sa1100_init); 330 331 void __init sa11x0_init_late(void) 332 { 333 sa11x0_pm_init(); 334 } 335 336 int __init sa11x0_register_fixed_regulator(int n, 337 struct fixed_voltage_config *cfg, 338 struct regulator_consumer_supply *supplies, unsigned num_supplies, 339 bool uses_gpio) 340 { 341 struct regulator_init_data *id; 342 343 cfg->init_data = id = kzalloc(sizeof(*cfg->init_data), GFP_KERNEL); 344 if (!cfg->init_data) 345 return -ENOMEM; 346 347 if (!uses_gpio) 348 id->constraints.always_on = 1; 349 id->constraints.name = cfg->supply_name; 350 id->constraints.min_uV = cfg->microvolts; 351 id->constraints.max_uV = cfg->microvolts; 352 id->constraints.valid_modes_mask = REGULATOR_MODE_NORMAL; 353 id->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; 354 id->consumer_supplies = supplies; 355 id->num_consumer_supplies = num_supplies; 356 357 platform_device_register_resndata(NULL, "reg-fixed-voltage", n, 358 NULL, 0, cfg, sizeof(*cfg)); 359 return 0; 360 } 361 362 /* 363 * Common I/O mapping: 364 * 365 * Typically, static virtual address mappings are as follow: 366 * 367 * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.) 368 * 0xf4000000-0xf4ffffff: SA-1111 369 * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area) 370 * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above) 371 * 0xffff0000-0xffff0fff: SA1100 exception vectors 372 * 0xffff2000-0xffff2fff: Minicache copy_user_page area 373 * 374 * Below 0xe8000000 is reserved for vm allocation. 375 * 376 * The machine specific code must provide the extra mapping beside the 377 * default mapping provided here. 378 */ 379 380 static struct map_desc standard_io_desc[] __initdata = { 381 { /* PCM */ 382 .virtual = 0xf8000000, 383 .pfn = __phys_to_pfn(0x80000000), 384 .length = 0x00100000, 385 .type = MT_DEVICE 386 }, { /* SCM */ 387 .virtual = 0xfa000000, 388 .pfn = __phys_to_pfn(0x90000000), 389 .length = 0x00100000, 390 .type = MT_DEVICE 391 }, { /* MER */ 392 .virtual = 0xfc000000, 393 .pfn = __phys_to_pfn(0xa0000000), 394 .length = 0x00100000, 395 .type = MT_DEVICE 396 }, { /* LCD + DMA */ 397 .virtual = 0xfe000000, 398 .pfn = __phys_to_pfn(0xb0000000), 399 .length = 0x00200000, 400 .type = MT_DEVICE 401 }, 402 }; 403 404 void __init sa1100_map_io(void) 405 { 406 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 407 } 408 409 void __init sa1100_timer_init(void) 410 { 411 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000)); 412 } 413 414 static struct resource irq_resource = 415 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); 416 417 void __init sa1100_init_irq(void) 418 { 419 request_resource(&iomem_resource, &irq_resource); 420 421 sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start); 422 423 sa1100_init_gpio(); 424 sa11xx_clk_init(); 425 } 426 427 /* 428 * Disable the memory bus request/grant signals on the SA1110 to 429 * ensure that we don't receive spurious memory requests. We set 430 * the MBGNT signal false to ensure the SA1111 doesn't own the 431 * SDRAM bus. 432 */ 433 void sa1110_mb_disable(void) 434 { 435 unsigned long flags; 436 437 local_irq_save(flags); 438 439 PGSR &= ~GPIO_MBGNT; 440 GPCR = GPIO_MBGNT; 441 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 442 443 GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ); 444 445 local_irq_restore(flags); 446 } 447 448 /* 449 * If the system is going to use the SA-1111 DMA engines, set up 450 * the memory bus request/grant pins. 451 */ 452 void sa1110_mb_enable(void) 453 { 454 unsigned long flags; 455 456 local_irq_save(flags); 457 458 PGSR &= ~GPIO_MBGNT; 459 GPCR = GPIO_MBGNT; 460 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 461 462 GAFR |= (GPIO_MBGNT | GPIO_MBREQ); 463 TUCR |= TUCR_MR; 464 465 local_irq_restore(flags); 466 } 467 468 int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on) 469 { 470 if (on) 471 PWER |= BIT(gpio); 472 else 473 PWER &= ~BIT(gpio); 474 475 return 0; 476 } 477 478 int sa11x0_sc_set_wake(unsigned int irq, unsigned int on) 479 { 480 if (BIT(irq) != IC_RTCAlrm) 481 return -EINVAL; 482 483 if (on) 484 PWER |= PWER_RTC; 485 else 486 PWER &= ~PWER_RTC; 487 488 return 0; 489 } 490