1 /* 2 * linux/arch/arm/mach-sa1100/generic.c 3 * 4 * Author: Nicolas Pitre 5 * 6 * Code common to all SA11x0 machines. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/cpufreq.h> 18 #include <linux/ioport.h> 19 #include <linux/sched.h> /* just for sched_clock() - funny that */ 20 #include <linux/platform_device.h> 21 22 #include <asm/div64.h> 23 #include <asm/cnt32_to_63.h> 24 #include <asm/hardware.h> 25 #include <asm/system.h> 26 #include <asm/pgtable.h> 27 #include <asm/mach/map.h> 28 #include <asm/mach/flash.h> 29 #include <asm/irq.h> 30 31 #include "generic.h" 32 33 #define NR_FREQS 16 34 35 /* 36 * This table is setup for a 3.6864MHz Crystal. 37 */ 38 static const unsigned short cclk_frequency_100khz[NR_FREQS] = { 39 590, /* 59.0 MHz */ 40 737, /* 73.7 MHz */ 41 885, /* 88.5 MHz */ 42 1032, /* 103.2 MHz */ 43 1180, /* 118.0 MHz */ 44 1327, /* 132.7 MHz */ 45 1475, /* 147.5 MHz */ 46 1622, /* 162.2 MHz */ 47 1769, /* 176.9 MHz */ 48 1917, /* 191.7 MHz */ 49 2064, /* 206.4 MHz */ 50 2212, /* 221.2 MHz */ 51 2359, /* 235.9 MHz */ 52 2507, /* 250.7 MHz */ 53 2654, /* 265.4 MHz */ 54 2802 /* 280.2 MHz */ 55 }; 56 57 #if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110) 58 /* rounds up(!) */ 59 unsigned int sa11x0_freq_to_ppcr(unsigned int khz) 60 { 61 int i; 62 63 khz /= 100; 64 65 for (i = 0; i < NR_FREQS; i++) 66 if (cclk_frequency_100khz[i] >= khz) 67 break; 68 69 return i; 70 } 71 72 unsigned int sa11x0_ppcr_to_freq(unsigned int idx) 73 { 74 unsigned int freq = 0; 75 if (idx < NR_FREQS) 76 freq = cclk_frequency_100khz[idx] * 100; 77 return freq; 78 } 79 80 81 /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on 82 * this platform, anyway. 83 */ 84 int sa11x0_verify_speed(struct cpufreq_policy *policy) 85 { 86 unsigned int tmp; 87 if (policy->cpu) 88 return -EINVAL; 89 90 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); 91 92 /* make sure that at least one frequency is within the policy */ 93 tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100; 94 if (tmp > policy->max) 95 policy->max = tmp; 96 97 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); 98 99 return 0; 100 } 101 102 unsigned int sa11x0_getspeed(unsigned int cpu) 103 { 104 if (cpu) 105 return 0; 106 return cclk_frequency_100khz[PPCR & 0xf] * 100; 107 } 108 109 #else 110 /* 111 * We still need to provide this so building without cpufreq works. 112 */ 113 unsigned int cpufreq_get(unsigned int cpu) 114 { 115 return cclk_frequency_100khz[PPCR & 0xf] * 100; 116 } 117 EXPORT_SYMBOL(cpufreq_get); 118 #endif 119 120 /* 121 * This is the SA11x0 sched_clock implementation. This has 122 * a resolution of 271ns, and a maximum value of 32025597s (370 days). 123 * 124 * The return value is guaranteed to be monotonic in that range as 125 * long as there is always less than 582 seconds between successive 126 * calls to this function. 127 * 128 * ( * 1E9 / 3686400 => * 78125 / 288) 129 */ 130 unsigned long long sched_clock(void) 131 { 132 unsigned long long v = cnt32_to_63(OSCR); 133 134 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ 135 v *= 78125<<1; 136 do_div(v, 288<<1); 137 138 return v; 139 } 140 141 int gpio_direction_input(unsigned gpio) 142 { 143 unsigned long flags; 144 145 if (gpio > GPIO_MAX) 146 return -EINVAL; 147 148 local_irq_save(flags); 149 GPDR &= ~GPIO_GPIO(gpio); 150 local_irq_restore(flags); 151 return 0; 152 } 153 154 EXPORT_SYMBOL(gpio_direction_input); 155 156 int gpio_direction_output(unsigned gpio) 157 { 158 unsigned long flags; 159 160 if (gpio > GPIO_MAX) 161 return -EINVAL; 162 163 local_irq_save(flags); 164 GPDR |= GPIO_GPIO(gpio); 165 local_irq_restore(flags); 166 return 0; 167 } 168 169 EXPORT_SYMBOL(gpio_direction_output); 170 171 /* 172 * Default power-off for SA1100 173 */ 174 static void sa1100_power_off(void) 175 { 176 mdelay(100); 177 local_irq_disable(); 178 /* disable internal oscillator, float CS lines */ 179 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); 180 /* enable wake-up on GPIO0 (Assabet...) */ 181 PWER = GFER = GRER = 1; 182 /* 183 * set scratchpad to zero, just in case it is used as a 184 * restart address by the bootloader. 185 */ 186 PSPR = 0; 187 /* enter sleep mode */ 188 PMCR = PMCR_SF; 189 } 190 191 static struct resource sa11x0udc_resources[] = { 192 [0] = { 193 .start = 0x80000000, 194 .end = 0x8000ffff, 195 .flags = IORESOURCE_MEM, 196 }, 197 }; 198 199 static u64 sa11x0udc_dma_mask = 0xffffffffUL; 200 201 static struct platform_device sa11x0udc_device = { 202 .name = "sa11x0-udc", 203 .id = -1, 204 .dev = { 205 .dma_mask = &sa11x0udc_dma_mask, 206 .coherent_dma_mask = 0xffffffff, 207 }, 208 .num_resources = ARRAY_SIZE(sa11x0udc_resources), 209 .resource = sa11x0udc_resources, 210 }; 211 212 static struct resource sa11x0uart1_resources[] = { 213 [0] = { 214 .start = 0x80010000, 215 .end = 0x8001ffff, 216 .flags = IORESOURCE_MEM, 217 }, 218 }; 219 220 static struct platform_device sa11x0uart1_device = { 221 .name = "sa11x0-uart", 222 .id = 1, 223 .num_resources = ARRAY_SIZE(sa11x0uart1_resources), 224 .resource = sa11x0uart1_resources, 225 }; 226 227 static struct resource sa11x0uart3_resources[] = { 228 [0] = { 229 .start = 0x80050000, 230 .end = 0x8005ffff, 231 .flags = IORESOURCE_MEM, 232 }, 233 }; 234 235 static struct platform_device sa11x0uart3_device = { 236 .name = "sa11x0-uart", 237 .id = 3, 238 .num_resources = ARRAY_SIZE(sa11x0uart3_resources), 239 .resource = sa11x0uart3_resources, 240 }; 241 242 static struct resource sa11x0mcp_resources[] = { 243 [0] = { 244 .start = 0x80060000, 245 .end = 0x8006ffff, 246 .flags = IORESOURCE_MEM, 247 }, 248 }; 249 250 static u64 sa11x0mcp_dma_mask = 0xffffffffUL; 251 252 static struct platform_device sa11x0mcp_device = { 253 .name = "sa11x0-mcp", 254 .id = -1, 255 .dev = { 256 .dma_mask = &sa11x0mcp_dma_mask, 257 .coherent_dma_mask = 0xffffffff, 258 }, 259 .num_resources = ARRAY_SIZE(sa11x0mcp_resources), 260 .resource = sa11x0mcp_resources, 261 }; 262 263 void sa11x0_set_mcp_data(struct mcp_plat_data *data) 264 { 265 sa11x0mcp_device.dev.platform_data = data; 266 } 267 268 static struct resource sa11x0ssp_resources[] = { 269 [0] = { 270 .start = 0x80070000, 271 .end = 0x8007ffff, 272 .flags = IORESOURCE_MEM, 273 }, 274 }; 275 276 static u64 sa11x0ssp_dma_mask = 0xffffffffUL; 277 278 static struct platform_device sa11x0ssp_device = { 279 .name = "sa11x0-ssp", 280 .id = -1, 281 .dev = { 282 .dma_mask = &sa11x0ssp_dma_mask, 283 .coherent_dma_mask = 0xffffffff, 284 }, 285 .num_resources = ARRAY_SIZE(sa11x0ssp_resources), 286 .resource = sa11x0ssp_resources, 287 }; 288 289 static struct resource sa11x0fb_resources[] = { 290 [0] = { 291 .start = 0xb0100000, 292 .end = 0xb010ffff, 293 .flags = IORESOURCE_MEM, 294 }, 295 [1] = { 296 .start = IRQ_LCD, 297 .end = IRQ_LCD, 298 .flags = IORESOURCE_IRQ, 299 }, 300 }; 301 302 static struct platform_device sa11x0fb_device = { 303 .name = "sa11x0-fb", 304 .id = -1, 305 .dev = { 306 .coherent_dma_mask = 0xffffffff, 307 }, 308 .num_resources = ARRAY_SIZE(sa11x0fb_resources), 309 .resource = sa11x0fb_resources, 310 }; 311 312 static struct platform_device sa11x0pcmcia_device = { 313 .name = "sa11x0-pcmcia", 314 .id = -1, 315 }; 316 317 static struct platform_device sa11x0mtd_device = { 318 .name = "flash", 319 .id = -1, 320 }; 321 322 void sa11x0_set_flash_data(struct flash_platform_data *flash, 323 struct resource *res, int nr) 324 { 325 flash->name = "sa1100"; 326 sa11x0mtd_device.dev.platform_data = flash; 327 sa11x0mtd_device.resource = res; 328 sa11x0mtd_device.num_resources = nr; 329 } 330 331 static struct resource sa11x0ir_resources[] = { 332 { 333 .start = __PREG(Ser2UTCR0), 334 .end = __PREG(Ser2UTCR0) + 0x24 - 1, 335 .flags = IORESOURCE_MEM, 336 }, { 337 .start = __PREG(Ser2HSCR0), 338 .end = __PREG(Ser2HSCR0) + 0x1c - 1, 339 .flags = IORESOURCE_MEM, 340 }, { 341 .start = __PREG(Ser2HSCR2), 342 .end = __PREG(Ser2HSCR2) + 0x04 - 1, 343 .flags = IORESOURCE_MEM, 344 }, { 345 .start = IRQ_Ser2ICP, 346 .end = IRQ_Ser2ICP, 347 .flags = IORESOURCE_IRQ, 348 } 349 }; 350 351 static struct platform_device sa11x0ir_device = { 352 .name = "sa11x0-ir", 353 .id = -1, 354 .num_resources = ARRAY_SIZE(sa11x0ir_resources), 355 .resource = sa11x0ir_resources, 356 }; 357 358 void sa11x0_set_irda_data(struct irda_platform_data *irda) 359 { 360 sa11x0ir_device.dev.platform_data = irda; 361 } 362 363 static struct platform_device sa11x0rtc_device = { 364 .name = "sa1100-rtc", 365 .id = -1, 366 }; 367 368 static struct platform_device *sa11x0_devices[] __initdata = { 369 &sa11x0udc_device, 370 &sa11x0uart1_device, 371 &sa11x0uart3_device, 372 &sa11x0mcp_device, 373 &sa11x0ssp_device, 374 &sa11x0pcmcia_device, 375 &sa11x0fb_device, 376 &sa11x0mtd_device, 377 &sa11x0rtc_device, 378 }; 379 380 static int __init sa1100_init(void) 381 { 382 pm_power_off = sa1100_power_off; 383 384 if (sa11x0ir_device.dev.platform_data) 385 platform_device_register(&sa11x0ir_device); 386 387 return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices)); 388 } 389 390 arch_initcall(sa1100_init); 391 392 void (*sa1100fb_backlight_power)(int on); 393 void (*sa1100fb_lcd_power)(int on); 394 395 EXPORT_SYMBOL(sa1100fb_backlight_power); 396 EXPORT_SYMBOL(sa1100fb_lcd_power); 397 398 399 /* 400 * Common I/O mapping: 401 * 402 * Typically, static virtual address mappings are as follow: 403 * 404 * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.) 405 * 0xf4000000-0xf4ffffff: SA-1111 406 * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area) 407 * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above) 408 * 0xffff0000-0xffff0fff: SA1100 exception vectors 409 * 0xffff2000-0xffff2fff: Minicache copy_user_page area 410 * 411 * Below 0xe8000000 is reserved for vm allocation. 412 * 413 * The machine specific code must provide the extra mapping beside the 414 * default mapping provided here. 415 */ 416 417 static struct map_desc standard_io_desc[] __initdata = { 418 { /* PCM */ 419 .virtual = 0xf8000000, 420 .pfn = __phys_to_pfn(0x80000000), 421 .length = 0x00100000, 422 .type = MT_DEVICE 423 }, { /* SCM */ 424 .virtual = 0xfa000000, 425 .pfn = __phys_to_pfn(0x90000000), 426 .length = 0x00100000, 427 .type = MT_DEVICE 428 }, { /* MER */ 429 .virtual = 0xfc000000, 430 .pfn = __phys_to_pfn(0xa0000000), 431 .length = 0x00100000, 432 .type = MT_DEVICE 433 }, { /* LCD + DMA */ 434 .virtual = 0xfe000000, 435 .pfn = __phys_to_pfn(0xb0000000), 436 .length = 0x00200000, 437 .type = MT_DEVICE 438 }, 439 }; 440 441 void __init sa1100_map_io(void) 442 { 443 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 444 } 445 446 /* 447 * Disable the memory bus request/grant signals on the SA1110 to 448 * ensure that we don't receive spurious memory requests. We set 449 * the MBGNT signal false to ensure the SA1111 doesn't own the 450 * SDRAM bus. 451 */ 452 void __init sa1110_mb_disable(void) 453 { 454 unsigned long flags; 455 456 local_irq_save(flags); 457 458 PGSR &= ~GPIO_MBGNT; 459 GPCR = GPIO_MBGNT; 460 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 461 462 GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ); 463 464 local_irq_restore(flags); 465 } 466 467 /* 468 * If the system is going to use the SA-1111 DMA engines, set up 469 * the memory bus request/grant pins. 470 */ 471 void __init sa1110_mb_enable(void) 472 { 473 unsigned long flags; 474 475 local_irq_save(flags); 476 477 PGSR &= ~GPIO_MBGNT; 478 GPCR = GPIO_MBGNT; 479 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 480 481 GAFR |= (GPIO_MBGNT | GPIO_MBREQ); 482 TUCR |= TUCR_MR; 483 484 local_irq_restore(flags); 485 } 486 487