1 /* 2 * linux/arch/arm/mach-sa1100/generic.c 3 * 4 * Author: Nicolas Pitre 5 * 6 * Code common to all SA11x0 machines. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 #include <linux/gpio.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/cpufreq.h> 19 #include <linux/ioport.h> 20 #include <linux/platform_device.h> 21 22 #include <asm/div64.h> 23 #include <mach/hardware.h> 24 #include <asm/system.h> 25 #include <asm/mach/map.h> 26 #include <asm/mach/flash.h> 27 #include <asm/irq.h> 28 29 #include "generic.h" 30 31 unsigned int reset_status; 32 EXPORT_SYMBOL(reset_status); 33 34 #define NR_FREQS 16 35 36 /* 37 * This table is setup for a 3.6864MHz Crystal. 38 */ 39 static const unsigned short cclk_frequency_100khz[NR_FREQS] = { 40 590, /* 59.0 MHz */ 41 737, /* 73.7 MHz */ 42 885, /* 88.5 MHz */ 43 1032, /* 103.2 MHz */ 44 1180, /* 118.0 MHz */ 45 1327, /* 132.7 MHz */ 46 1475, /* 147.5 MHz */ 47 1622, /* 162.2 MHz */ 48 1769, /* 176.9 MHz */ 49 1917, /* 191.7 MHz */ 50 2064, /* 206.4 MHz */ 51 2212, /* 221.2 MHz */ 52 2359, /* 235.9 MHz */ 53 2507, /* 250.7 MHz */ 54 2654, /* 265.4 MHz */ 55 2802 /* 280.2 MHz */ 56 }; 57 58 /* rounds up(!) */ 59 unsigned int sa11x0_freq_to_ppcr(unsigned int khz) 60 { 61 int i; 62 63 khz /= 100; 64 65 for (i = 0; i < NR_FREQS; i++) 66 if (cclk_frequency_100khz[i] >= khz) 67 break; 68 69 return i; 70 } 71 72 unsigned int sa11x0_ppcr_to_freq(unsigned int idx) 73 { 74 unsigned int freq = 0; 75 if (idx < NR_FREQS) 76 freq = cclk_frequency_100khz[idx] * 100; 77 return freq; 78 } 79 80 81 /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on 82 * this platform, anyway. 83 */ 84 int sa11x0_verify_speed(struct cpufreq_policy *policy) 85 { 86 unsigned int tmp; 87 if (policy->cpu) 88 return -EINVAL; 89 90 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); 91 92 /* make sure that at least one frequency is within the policy */ 93 tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100; 94 if (tmp > policy->max) 95 policy->max = tmp; 96 97 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); 98 99 return 0; 100 } 101 102 unsigned int sa11x0_getspeed(unsigned int cpu) 103 { 104 if (cpu) 105 return 0; 106 return cclk_frequency_100khz[PPCR & 0xf] * 100; 107 } 108 109 /* 110 * Default power-off for SA1100 111 */ 112 static void sa1100_power_off(void) 113 { 114 mdelay(100); 115 local_irq_disable(); 116 /* disable internal oscillator, float CS lines */ 117 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); 118 /* enable wake-up on GPIO0 (Assabet...) */ 119 PWER = GFER = GRER = 1; 120 /* 121 * set scratchpad to zero, just in case it is used as a 122 * restart address by the bootloader. 123 */ 124 PSPR = 0; 125 /* enter sleep mode */ 126 PMCR = PMCR_SF; 127 } 128 129 void sa11x0_restart(char mode, const char *cmd) 130 { 131 if (mode == 's') { 132 /* Jump into ROM at address 0 */ 133 soft_restart(0); 134 } else { 135 /* Use on-chip reset capability */ 136 RSRR = RSRR_SWR; 137 } 138 } 139 140 static void sa11x0_register_device(struct platform_device *dev, void *data) 141 { 142 int err; 143 dev->dev.platform_data = data; 144 err = platform_device_register(dev); 145 if (err) 146 printk(KERN_ERR "Unable to register device %s: %d\n", 147 dev->name, err); 148 } 149 150 151 static struct resource sa11x0udc_resources[] = { 152 [0] = { 153 .start = __PREG(Ser0UDCCR), 154 .end = __PREG(Ser0UDCCR) + 0xffff, 155 .flags = IORESOURCE_MEM, 156 }, 157 [1] = { 158 .start = IRQ_Ser0UDC, 159 .end = IRQ_Ser0UDC, 160 .flags = IORESOURCE_IRQ, 161 }, 162 }; 163 164 static u64 sa11x0udc_dma_mask = 0xffffffffUL; 165 166 static struct platform_device sa11x0udc_device = { 167 .name = "sa11x0-udc", 168 .id = -1, 169 .dev = { 170 .dma_mask = &sa11x0udc_dma_mask, 171 .coherent_dma_mask = 0xffffffff, 172 }, 173 .num_resources = ARRAY_SIZE(sa11x0udc_resources), 174 .resource = sa11x0udc_resources, 175 }; 176 177 static struct resource sa11x0uart1_resources[] = { 178 [0] = { 179 .start = __PREG(Ser1UTCR0), 180 .end = __PREG(Ser1UTCR0) + 0xffff, 181 .flags = IORESOURCE_MEM, 182 }, 183 [1] = { 184 .start = IRQ_Ser1UART, 185 .end = IRQ_Ser1UART, 186 .flags = IORESOURCE_IRQ, 187 }, 188 }; 189 190 static struct platform_device sa11x0uart1_device = { 191 .name = "sa11x0-uart", 192 .id = 1, 193 .num_resources = ARRAY_SIZE(sa11x0uart1_resources), 194 .resource = sa11x0uart1_resources, 195 }; 196 197 static struct resource sa11x0uart3_resources[] = { 198 [0] = { 199 .start = __PREG(Ser3UTCR0), 200 .end = __PREG(Ser3UTCR0) + 0xffff, 201 .flags = IORESOURCE_MEM, 202 }, 203 [1] = { 204 .start = IRQ_Ser3UART, 205 .end = IRQ_Ser3UART, 206 .flags = IORESOURCE_IRQ, 207 }, 208 }; 209 210 static struct platform_device sa11x0uart3_device = { 211 .name = "sa11x0-uart", 212 .id = 3, 213 .num_resources = ARRAY_SIZE(sa11x0uart3_resources), 214 .resource = sa11x0uart3_resources, 215 }; 216 217 static struct resource sa11x0mcp_resources[] = { 218 [0] = { 219 .start = __PREG(Ser4MCCR0), 220 .end = __PREG(Ser4MCCR0) + 0xffff, 221 .flags = IORESOURCE_MEM, 222 }, 223 [1] = { 224 .start = IRQ_Ser4MCP, 225 .end = IRQ_Ser4MCP, 226 .flags = IORESOURCE_IRQ, 227 }, 228 }; 229 230 static u64 sa11x0mcp_dma_mask = 0xffffffffUL; 231 232 static struct platform_device sa11x0mcp_device = { 233 .name = "sa11x0-mcp", 234 .id = -1, 235 .dev = { 236 .dma_mask = &sa11x0mcp_dma_mask, 237 .coherent_dma_mask = 0xffffffff, 238 }, 239 .num_resources = ARRAY_SIZE(sa11x0mcp_resources), 240 .resource = sa11x0mcp_resources, 241 }; 242 243 void sa11x0_register_mcp(struct mcp_plat_data *data) 244 { 245 sa11x0_register_device(&sa11x0mcp_device, data); 246 } 247 248 static struct resource sa11x0ssp_resources[] = { 249 [0] = { 250 .start = 0x80070000, 251 .end = 0x8007ffff, 252 .flags = IORESOURCE_MEM, 253 }, 254 [1] = { 255 .start = IRQ_Ser4SSP, 256 .end = IRQ_Ser4SSP, 257 .flags = IORESOURCE_IRQ, 258 }, 259 }; 260 261 static u64 sa11x0ssp_dma_mask = 0xffffffffUL; 262 263 static struct platform_device sa11x0ssp_device = { 264 .name = "sa11x0-ssp", 265 .id = -1, 266 .dev = { 267 .dma_mask = &sa11x0ssp_dma_mask, 268 .coherent_dma_mask = 0xffffffff, 269 }, 270 .num_resources = ARRAY_SIZE(sa11x0ssp_resources), 271 .resource = sa11x0ssp_resources, 272 }; 273 274 static struct resource sa11x0fb_resources[] = { 275 [0] = { 276 .start = 0xb0100000, 277 .end = 0xb010ffff, 278 .flags = IORESOURCE_MEM, 279 }, 280 [1] = { 281 .start = IRQ_LCD, 282 .end = IRQ_LCD, 283 .flags = IORESOURCE_IRQ, 284 }, 285 }; 286 287 static struct platform_device sa11x0fb_device = { 288 .name = "sa11x0-fb", 289 .id = -1, 290 .dev = { 291 .coherent_dma_mask = 0xffffffff, 292 }, 293 .num_resources = ARRAY_SIZE(sa11x0fb_resources), 294 .resource = sa11x0fb_resources, 295 }; 296 297 static struct platform_device sa11x0pcmcia_device = { 298 .name = "sa11x0-pcmcia", 299 .id = -1, 300 }; 301 302 static struct platform_device sa11x0mtd_device = { 303 .name = "sa1100-mtd", 304 .id = -1, 305 }; 306 307 void sa11x0_register_mtd(struct flash_platform_data *flash, 308 struct resource *res, int nr) 309 { 310 flash->name = "sa1100"; 311 sa11x0mtd_device.resource = res; 312 sa11x0mtd_device.num_resources = nr; 313 sa11x0_register_device(&sa11x0mtd_device, flash); 314 } 315 316 static struct resource sa11x0ir_resources[] = { 317 { 318 .start = __PREG(Ser2UTCR0), 319 .end = __PREG(Ser2UTCR0) + 0x24 - 1, 320 .flags = IORESOURCE_MEM, 321 }, { 322 .start = __PREG(Ser2HSCR0), 323 .end = __PREG(Ser2HSCR0) + 0x1c - 1, 324 .flags = IORESOURCE_MEM, 325 }, { 326 .start = __PREG(Ser2HSCR2), 327 .end = __PREG(Ser2HSCR2) + 0x04 - 1, 328 .flags = IORESOURCE_MEM, 329 }, { 330 .start = IRQ_Ser2ICP, 331 .end = IRQ_Ser2ICP, 332 .flags = IORESOURCE_IRQ, 333 } 334 }; 335 336 static struct platform_device sa11x0ir_device = { 337 .name = "sa11x0-ir", 338 .id = -1, 339 .num_resources = ARRAY_SIZE(sa11x0ir_resources), 340 .resource = sa11x0ir_resources, 341 }; 342 343 void sa11x0_register_irda(struct irda_platform_data *irda) 344 { 345 sa11x0_register_device(&sa11x0ir_device, irda); 346 } 347 348 static struct platform_device sa11x0rtc_device = { 349 .name = "sa1100-rtc", 350 .id = -1, 351 }; 352 353 static struct platform_device *sa11x0_devices[] __initdata = { 354 &sa11x0udc_device, 355 &sa11x0uart1_device, 356 &sa11x0uart3_device, 357 &sa11x0ssp_device, 358 &sa11x0pcmcia_device, 359 &sa11x0fb_device, 360 &sa11x0rtc_device, 361 }; 362 363 static int __init sa1100_init(void) 364 { 365 pm_power_off = sa1100_power_off; 366 return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices)); 367 } 368 369 arch_initcall(sa1100_init); 370 371 void (*sa1100fb_backlight_power)(int on); 372 void (*sa1100fb_lcd_power)(int on); 373 374 EXPORT_SYMBOL(sa1100fb_backlight_power); 375 EXPORT_SYMBOL(sa1100fb_lcd_power); 376 377 378 /* 379 * Common I/O mapping: 380 * 381 * Typically, static virtual address mappings are as follow: 382 * 383 * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.) 384 * 0xf4000000-0xf4ffffff: SA-1111 385 * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area) 386 * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above) 387 * 0xffff0000-0xffff0fff: SA1100 exception vectors 388 * 0xffff2000-0xffff2fff: Minicache copy_user_page area 389 * 390 * Below 0xe8000000 is reserved for vm allocation. 391 * 392 * The machine specific code must provide the extra mapping beside the 393 * default mapping provided here. 394 */ 395 396 static struct map_desc standard_io_desc[] __initdata = { 397 { /* PCM */ 398 .virtual = 0xf8000000, 399 .pfn = __phys_to_pfn(0x80000000), 400 .length = 0x00100000, 401 .type = MT_DEVICE 402 }, { /* SCM */ 403 .virtual = 0xfa000000, 404 .pfn = __phys_to_pfn(0x90000000), 405 .length = 0x00100000, 406 .type = MT_DEVICE 407 }, { /* MER */ 408 .virtual = 0xfc000000, 409 .pfn = __phys_to_pfn(0xa0000000), 410 .length = 0x00100000, 411 .type = MT_DEVICE 412 }, { /* LCD + DMA */ 413 .virtual = 0xfe000000, 414 .pfn = __phys_to_pfn(0xb0000000), 415 .length = 0x00200000, 416 .type = MT_DEVICE 417 }, 418 }; 419 420 void __init sa1100_map_io(void) 421 { 422 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 423 } 424 425 /* 426 * Disable the memory bus request/grant signals on the SA1110 to 427 * ensure that we don't receive spurious memory requests. We set 428 * the MBGNT signal false to ensure the SA1111 doesn't own the 429 * SDRAM bus. 430 */ 431 void __init sa1110_mb_disable(void) 432 { 433 unsigned long flags; 434 435 local_irq_save(flags); 436 437 PGSR &= ~GPIO_MBGNT; 438 GPCR = GPIO_MBGNT; 439 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 440 441 GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ); 442 443 local_irq_restore(flags); 444 } 445 446 /* 447 * If the system is going to use the SA-1111 DMA engines, set up 448 * the memory bus request/grant pins. 449 */ 450 void __devinit sa1110_mb_enable(void) 451 { 452 unsigned long flags; 453 454 local_irq_save(flags); 455 456 PGSR &= ~GPIO_MBGNT; 457 GPCR = GPIO_MBGNT; 458 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 459 460 GAFR |= (GPIO_MBGNT | GPIO_MBREQ); 461 TUCR |= TUCR_MR; 462 463 local_irq_restore(flags); 464 } 465 466