1*71b9114dSArnd Bergmann /* SPDX-License-Identifier: GPL-2.0-only */ 2*71b9114dSArnd Bergmann /* 3*71b9114dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 4*71b9114dSArnd Bergmann * Copyright 2008 Simtec Electronics 5*71b9114dSArnd Bergmann * http://armlinux.simtec.co.uk/ 6*71b9114dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 7*71b9114dSArnd Bergmann * 8*71b9114dSArnd Bergmann * S3C - USB2.0 Highspeed/OtG device PHY registers 9*71b9114dSArnd Bergmann */ 10*71b9114dSArnd Bergmann 11*71b9114dSArnd Bergmann /* Note, this is a separate header file as some of the clock framework 12*71b9114dSArnd Bergmann * needs to touch this if the clk_48m is used as the USB OHCI or other 13*71b9114dSArnd Bergmann * peripheral source. 14*71b9114dSArnd Bergmann */ 15*71b9114dSArnd Bergmann 16*71b9114dSArnd Bergmann #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H 17*71b9114dSArnd Bergmann #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__ 18*71b9114dSArnd Bergmann 19*71b9114dSArnd Bergmann /* S3C64XX_PA_USB_HSPHY */ 20*71b9114dSArnd Bergmann 21*71b9114dSArnd Bergmann #define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) 22*71b9114dSArnd Bergmann 23*71b9114dSArnd Bergmann #define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) 24*71b9114dSArnd Bergmann #define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) 25*71b9114dSArnd Bergmann #define S3C_PHYPWR_OTG_DISABLE (1 << 4) 26*71b9114dSArnd Bergmann #define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) 27*71b9114dSArnd Bergmann #define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) 28*71b9114dSArnd Bergmann 29*71b9114dSArnd Bergmann #define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) 30*71b9114dSArnd Bergmann #define S3C_PHYCLK_MODE_USB11 (1 << 6) 31*71b9114dSArnd Bergmann #define S3C_PHYCLK_EXT_OSC (1 << 5) 32*71b9114dSArnd Bergmann #define S3C_PHYCLK_CLK_FORCE (1 << 4) 33*71b9114dSArnd Bergmann #define S3C_PHYCLK_ID_PULL (1 << 2) 34*71b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0) 35*71b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_SHIFT (0) 36*71b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_48M (0x0 << 0) 37*71b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_12M (0x2 << 0) 38*71b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_24M (0x3 << 0) 39*71b9114dSArnd Bergmann 40*71b9114dSArnd Bergmann #define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) 41*71b9114dSArnd Bergmann #define S3C_RSTCON_PHYCLK (1 << 2) 42*71b9114dSArnd Bergmann #define S3C_RSTCON_HCLK (1 << 1) 43*71b9114dSArnd Bergmann #define S3C_RSTCON_PHY (1 << 0) 44*71b9114dSArnd Bergmann 45*71b9114dSArnd Bergmann #define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20) 46*71b9114dSArnd Bergmann 47*71b9114dSArnd Bergmann #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */ 48