1*c6ff132dSArnd Bergmann /* SPDX-License-Identifier: GPL-2.0 */ 2*c6ff132dSArnd Bergmann /* 3*c6ff132dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 4*c6ff132dSArnd Bergmann * Copyright 2008 Simtec Electronics 5*c6ff132dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 6*c6ff132dSArnd Bergmann * http://armlinux.simtec.co.uk/ 7*c6ff132dSArnd Bergmann * 8*c6ff132dSArnd Bergmann * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c 9*c6ff132dSArnd Bergmann */ 10*c6ff132dSArnd Bergmann 11*c6ff132dSArnd Bergmann #ifndef __MACH_S3C64XX_PM_CORE_H 12*c6ff132dSArnd Bergmann #define __MACH_S3C64XX_PM_CORE_H __FILE__ 13*c6ff132dSArnd Bergmann 14*c6ff132dSArnd Bergmann #include <linux/serial_s3c.h> 15*c6ff132dSArnd Bergmann #include <linux/delay.h> 16*c6ff132dSArnd Bergmann 17*c6ff132dSArnd Bergmann #include "regs-gpio.h" 18*c6ff132dSArnd Bergmann #include "regs-clock.h" 19*c6ff132dSArnd Bergmann #include "map.h" 20*c6ff132dSArnd Bergmann 21*c6ff132dSArnd Bergmann static inline void s3c_pm_debug_init_uart(void) 22*c6ff132dSArnd Bergmann { 23*c6ff132dSArnd Bergmann #ifdef CONFIG_SAMSUNG_PM_DEBUG 24*c6ff132dSArnd Bergmann u32 tmp = __raw_readl(S3C_PCLK_GATE); 25*c6ff132dSArnd Bergmann 26*c6ff132dSArnd Bergmann /* As a note, since the S3C64XX UARTs generally have multiple 27*c6ff132dSArnd Bergmann * clock sources, we simply enable PCLK at the moment and hope 28*c6ff132dSArnd Bergmann * that the resume settings for the UART are suitable for the 29*c6ff132dSArnd Bergmann * use with PCLK. 30*c6ff132dSArnd Bergmann */ 31*c6ff132dSArnd Bergmann 32*c6ff132dSArnd Bergmann tmp |= S3C_CLKCON_PCLK_UART0; 33*c6ff132dSArnd Bergmann tmp |= S3C_CLKCON_PCLK_UART1; 34*c6ff132dSArnd Bergmann tmp |= S3C_CLKCON_PCLK_UART2; 35*c6ff132dSArnd Bergmann tmp |= S3C_CLKCON_PCLK_UART3; 36*c6ff132dSArnd Bergmann 37*c6ff132dSArnd Bergmann __raw_writel(tmp, S3C_PCLK_GATE); 38*c6ff132dSArnd Bergmann udelay(10); 39*c6ff132dSArnd Bergmann #endif 40*c6ff132dSArnd Bergmann } 41*c6ff132dSArnd Bergmann 42*c6ff132dSArnd Bergmann static inline void s3c_pm_arch_prepare_irqs(void) 43*c6ff132dSArnd Bergmann { 44*c6ff132dSArnd Bergmann /* VIC should have already been taken care of */ 45*c6ff132dSArnd Bergmann 46*c6ff132dSArnd Bergmann /* clear any pending EINT0 interrupts */ 47*c6ff132dSArnd Bergmann __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); 48*c6ff132dSArnd Bergmann } 49*c6ff132dSArnd Bergmann 50*c6ff132dSArnd Bergmann static inline void s3c_pm_arch_stop_clocks(void) 51*c6ff132dSArnd Bergmann { 52*c6ff132dSArnd Bergmann } 53*c6ff132dSArnd Bergmann 54*c6ff132dSArnd Bergmann static inline void s3c_pm_arch_show_resume_irqs(void) 55*c6ff132dSArnd Bergmann { 56*c6ff132dSArnd Bergmann } 57*c6ff132dSArnd Bergmann 58*c6ff132dSArnd Bergmann /* make these defines, we currently do not have any need to change 59*c6ff132dSArnd Bergmann * the IRQ wake controls depending on the CPU we are running on */ 60*c6ff132dSArnd Bergmann #ifdef CONFIG_PM_SLEEP 61*c6ff132dSArnd Bergmann #define s3c_irqwake_eintallow ((1 << 28) - 1) 62*c6ff132dSArnd Bergmann #define s3c_irqwake_intallow (~0) 63*c6ff132dSArnd Bergmann #else 64*c6ff132dSArnd Bergmann #define s3c_irqwake_eintallow 0 65*c6ff132dSArnd Bergmann #define s3c_irqwake_intallow 0 66*c6ff132dSArnd Bergmann #endif 67*c6ff132dSArnd Bergmann 68*c6ff132dSArnd Bergmann static inline void s3c_pm_restored_gpios(void) 69*c6ff132dSArnd Bergmann { 70*c6ff132dSArnd Bergmann /* ensure sleep mode has been cleared from the system */ 71*c6ff132dSArnd Bergmann 72*c6ff132dSArnd Bergmann __raw_writel(0, S3C64XX_SLPEN); 73*c6ff132dSArnd Bergmann } 74*c6ff132dSArnd Bergmann 75*c6ff132dSArnd Bergmann static inline void samsung_pm_saved_gpios(void) 76*c6ff132dSArnd Bergmann { 77*c6ff132dSArnd Bergmann /* turn on the sleep mode and keep it there, as it seems that during 78*c6ff132dSArnd Bergmann * suspend the xCON registers get re-set and thus you can end up with 79*c6ff132dSArnd Bergmann * problems between going to sleep and resuming. 80*c6ff132dSArnd Bergmann */ 81*c6ff132dSArnd Bergmann 82*c6ff132dSArnd Bergmann __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); 83*c6ff132dSArnd Bergmann } 84*c6ff132dSArnd Bergmann #endif /* __MACH_S3C64XX_PM_CORE_H */ 85