1 /* 2 * Copyright (c) 2013 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/regmap.h> 23 #include <linux/mfd/syscon.h> 24 25 #include <linux/reset.h> 26 #include <linux/cpu.h> 27 #include <asm/cacheflush.h> 28 #include <asm/cp15.h> 29 #include <asm/smp_scu.h> 30 #include <asm/smp_plat.h> 31 #include <asm/mach/map.h> 32 33 #include "core.h" 34 35 static void __iomem *scu_base_addr; 36 static void __iomem *sram_base_addr; 37 static int ncores; 38 39 #define PMU_PWRDN_CON 0x08 40 #define PMU_PWRDN_ST 0x0c 41 42 #define PMU_PWRDN_SCU 4 43 44 static struct regmap *pmu; 45 46 static int pmu_power_domain_is_on(int pd) 47 { 48 u32 val; 49 int ret; 50 51 ret = regmap_read(pmu, PMU_PWRDN_ST, &val); 52 if (ret < 0) 53 return ret; 54 55 return !(val & BIT(pd)); 56 } 57 58 static struct reset_control *rockchip_get_core_reset(int cpu) 59 { 60 struct device *dev = get_cpu_device(cpu); 61 struct device_node *np; 62 63 /* The cpu device is only available after the initial core bringup */ 64 if (dev) 65 np = dev->of_node; 66 else 67 np = of_get_cpu_node(cpu, 0); 68 69 return of_reset_control_get(np, NULL); 70 } 71 72 static int pmu_set_power_domain(int pd, bool on) 73 { 74 u32 val = (on) ? 0 : BIT(pd); 75 struct reset_control *rstc = rockchip_get_core_reset(pd); 76 int ret; 77 78 if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { 79 pr_err("%s: could not get reset control for core %d\n", 80 __func__, pd); 81 return PTR_ERR(rstc); 82 } 83 84 /* 85 * We need to soft reset the cpu when we turn off the cpu power domain, 86 * or else the active processors might be stalled when the individual 87 * processor is powered down. 88 */ 89 if (!IS_ERR(rstc) && !on) 90 reset_control_assert(rstc); 91 92 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); 93 if (ret < 0) { 94 pr_err("%s: could not update power domain\n", __func__); 95 return ret; 96 } 97 98 ret = -1; 99 while (ret != on) { 100 ret = pmu_power_domain_is_on(pd); 101 if (ret < 0) { 102 pr_err("%s: could not read power domain state\n", 103 __func__); 104 return ret; 105 } 106 } 107 108 if (!IS_ERR(rstc)) { 109 if (on) 110 reset_control_deassert(rstc); 111 reset_control_put(rstc); 112 } 113 114 return 0; 115 } 116 117 /* 118 * Handling of CPU cores 119 */ 120 121 static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) 122 { 123 int ret; 124 125 if (!sram_base_addr || !pmu) { 126 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); 127 return -ENXIO; 128 } 129 130 if (cpu >= ncores) { 131 pr_err("%s: cpu %d outside maximum number of cpus %d\n", 132 __func__, cpu, ncores); 133 return -ENXIO; 134 } 135 136 /* start the core */ 137 ret = pmu_set_power_domain(0 + cpu, true); 138 if (ret < 0) 139 return ret; 140 141 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { 142 /* 143 * We communicate with the bootrom to active the cpus other 144 * than cpu0, after a blob of initialize code, they will 145 * stay at wfe state, once they are actived, they will check 146 * the mailbox: 147 * sram_base_addr + 4: 0xdeadbeaf 148 * sram_base_addr + 8: start address for pc 149 * The cpu0 need to wait the other cpus other than cpu0 entering 150 * the wfe state.The wait time is affected by many aspects. 151 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) 152 */ 153 mdelay(1); /* ensure the cpus other than cpu0 to startup */ 154 155 writel(virt_to_phys(secondary_startup), sram_base_addr + 8); 156 writel(0xDEADBEAF, sram_base_addr + 4); 157 dsb_sev(); 158 } 159 160 return 0; 161 } 162 163 /** 164 * rockchip_smp_prepare_sram - populate necessary sram block 165 * Starting cores execute the code residing at the start of the on-chip sram 166 * after power-on. Therefore make sure, this sram region is reserved and 167 * big enough. After this check, copy the trampoline code that directs the 168 * core to the real startup code in ram into the sram-region. 169 * @node: mmio-sram device node 170 */ 171 static int __init rockchip_smp_prepare_sram(struct device_node *node) 172 { 173 unsigned int trampoline_sz = &rockchip_secondary_trampoline_end - 174 &rockchip_secondary_trampoline; 175 struct resource res; 176 unsigned int rsize; 177 int ret; 178 179 ret = of_address_to_resource(node, 0, &res); 180 if (ret < 0) { 181 pr_err("%s: could not get address for node %s\n", 182 __func__, node->full_name); 183 return ret; 184 } 185 186 rsize = resource_size(&res); 187 if (rsize < trampoline_sz) { 188 pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n", 189 __func__, rsize, trampoline_sz); 190 return -EINVAL; 191 } 192 193 /* set the boot function for the sram code */ 194 rockchip_boot_fn = virt_to_phys(secondary_startup); 195 196 /* copy the trampoline to sram, that runs during startup of the core */ 197 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz); 198 flush_cache_all(); 199 outer_clean_range(0, trampoline_sz); 200 201 dsb_sev(); 202 203 return 0; 204 } 205 206 static const struct regmap_config rockchip_pmu_regmap_config = { 207 .reg_bits = 32, 208 .val_bits = 32, 209 .reg_stride = 4, 210 }; 211 212 static int __init rockchip_smp_prepare_pmu(void) 213 { 214 struct device_node *node; 215 void __iomem *pmu_base; 216 217 /* 218 * This function is only called via smp_ops->smp_prepare_cpu(). 219 * That only happens if a "/cpus" device tree node exists 220 * and has an "enable-method" property that selects the SMP 221 * operations defined herein. 222 */ 223 node = of_find_node_by_path("/cpus"); 224 225 pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu"); 226 of_node_put(node); 227 if (!IS_ERR(pmu)) 228 return 0; 229 230 pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu"); 231 if (!IS_ERR(pmu)) 232 return 0; 233 234 /* fallback, create our own regmap for the pmu area */ 235 pmu = NULL; 236 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu"); 237 if (!node) { 238 pr_err("%s: could not find pmu dt node\n", __func__); 239 return -ENODEV; 240 } 241 242 pmu_base = of_iomap(node, 0); 243 if (!pmu_base) { 244 pr_err("%s: could not map pmu registers\n", __func__); 245 return -ENOMEM; 246 } 247 248 pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config); 249 if (IS_ERR(pmu)) { 250 int ret = PTR_ERR(pmu); 251 252 iounmap(pmu_base); 253 pmu = NULL; 254 pr_err("%s: regmap init failed\n", __func__); 255 return ret; 256 } 257 258 return 0; 259 } 260 261 static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) 262 { 263 struct device_node *node; 264 unsigned int i; 265 266 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram"); 267 if (!node) { 268 pr_err("%s: could not find sram dt node\n", __func__); 269 return; 270 } 271 272 sram_base_addr = of_iomap(node, 0); 273 if (!sram_base_addr) { 274 pr_err("%s: could not map sram registers\n", __func__); 275 return; 276 } 277 278 if (rockchip_smp_prepare_pmu()) 279 return; 280 281 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 282 if (rockchip_smp_prepare_sram(node)) 283 return; 284 285 /* enable the SCU power domain */ 286 pmu_set_power_domain(PMU_PWRDN_SCU, true); 287 288 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); 289 if (!node) { 290 pr_err("%s: missing scu\n", __func__); 291 return; 292 } 293 294 scu_base_addr = of_iomap(node, 0); 295 if (!scu_base_addr) { 296 pr_err("%s: could not map scu registers\n", __func__); 297 return; 298 } 299 300 /* 301 * While the number of cpus is gathered from dt, also get the 302 * number of cores from the scu to verify this value when 303 * booting the cores. 304 */ 305 ncores = scu_get_core_count(scu_base_addr); 306 pr_err("%s: ncores %d\n", __func__, ncores); 307 308 scu_enable(scu_base_addr); 309 } else { 310 unsigned int l2ctlr; 311 312 asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); 313 ncores = ((l2ctlr >> 24) & 0x3) + 1; 314 } 315 316 /* Make sure that all cores except the first are really off */ 317 for (i = 1; i < ncores; i++) 318 pmu_set_power_domain(0 + i, false); 319 } 320 321 #ifdef CONFIG_HOTPLUG_CPU 322 static int rockchip_cpu_kill(unsigned int cpu) 323 { 324 /* 325 * We need a delay here to ensure that the dying CPU can finish 326 * executing v7_coherency_exit() and reach the WFI/WFE state 327 * prior to having the power domain disabled. 328 */ 329 mdelay(1); 330 331 pmu_set_power_domain(0 + cpu, false); 332 return 1; 333 } 334 335 static void rockchip_cpu_die(unsigned int cpu) 336 { 337 v7_exit_coherency_flush(louis); 338 while (1) 339 cpu_do_idle(); 340 } 341 #endif 342 343 static struct smp_operations rockchip_smp_ops __initdata = { 344 .smp_prepare_cpus = rockchip_smp_prepare_cpus, 345 .smp_boot_secondary = rockchip_boot_secondary, 346 #ifdef CONFIG_HOTPLUG_CPU 347 .cpu_kill = rockchip_cpu_kill, 348 .cpu_die = rockchip_cpu_die, 349 #endif 350 }; 351 352 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); 353