1 /* 2 * linux/arch/arm/mach-pxa/pxa27x.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Nov 05, 2002 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code specific to PXA27x aka Bulverde. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/platform_device.h> 19 #include <linux/sysdev.h> 20 21 #include <mach/hardware.h> 22 #include <asm/irq.h> 23 #include <mach/irqs.h> 24 #include <mach/pxa-regs.h> 25 #include <mach/pxa2xx-regs.h> 26 #include <mach/mfp-pxa27x.h> 27 #include <mach/reset.h> 28 #include <mach/ohci.h> 29 #include <mach/pm.h> 30 #include <mach/dma.h> 31 #include <mach/i2c.h> 32 33 #include "generic.h" 34 #include "devices.h" 35 #include "clock.h" 36 37 /* Crystal clock: 13MHz */ 38 #define BASE_CLK 13000000 39 40 /* 41 * Get the clock frequency as reflected by CCSR and the turbo flag. 42 * We assume these values have been applied via a fcs. 43 * If info is not 0 we also display the current settings. 44 */ 45 unsigned int pxa27x_get_clk_frequency_khz(int info) 46 { 47 unsigned long ccsr, clkcfg; 48 unsigned int l, L, m, M, n2, N, S; 49 int cccr_a, t, ht, b; 50 51 ccsr = CCSR; 52 cccr_a = CCCR & (1 << 25); 53 54 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ 55 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); 56 t = clkcfg & (1 << 0); 57 ht = clkcfg & (1 << 2); 58 b = clkcfg & (1 << 3); 59 60 l = ccsr & 0x1f; 61 n2 = (ccsr>>7) & 0xf; 62 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; 63 64 L = l * BASE_CLK; 65 N = (L * n2) / 2; 66 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); 67 S = (b) ? L : (L/2); 68 69 if (info) { 70 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", 71 L / 1000000, (L % 1000000) / 10000, l ); 72 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", 73 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5, 74 (t) ? "" : "in" ); 75 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n", 76 M / 1000000, (M % 1000000) / 10000, m ); 77 printk( KERN_INFO "System bus clock: %d.%02dMHz \n", 78 S / 1000000, (S % 1000000) / 10000 ); 79 } 80 81 return (t) ? (N/1000) : (L/1000); 82 } 83 84 /* 85 * Return the current mem clock frequency in units of 10kHz as 86 * reflected by CCCR[A], B, and L 87 */ 88 unsigned int pxa27x_get_memclk_frequency_10khz(void) 89 { 90 unsigned long ccsr, clkcfg; 91 unsigned int l, L, m, M; 92 int cccr_a, b; 93 94 ccsr = CCSR; 95 cccr_a = CCCR & (1 << 25); 96 97 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ 98 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); 99 b = clkcfg & (1 << 3); 100 101 l = ccsr & 0x1f; 102 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; 103 104 L = l * BASE_CLK; 105 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); 106 107 return (M / 10000); 108 } 109 110 /* 111 * Return the current LCD clock frequency in units of 10kHz as 112 */ 113 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) 114 { 115 unsigned long ccsr; 116 unsigned int l, L, k, K; 117 118 ccsr = CCSR; 119 120 l = ccsr & 0x1f; 121 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; 122 123 L = l * BASE_CLK; 124 K = L / k; 125 126 return (K / 10000); 127 } 128 129 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) 130 { 131 return pxa27x_get_lcdclk_frequency_10khz() * 10000; 132 } 133 134 static const struct clkops clk_pxa27x_lcd_ops = { 135 .enable = clk_cken_enable, 136 .disable = clk_cken_disable, 137 .getrate = clk_pxa27x_lcd_getrate, 138 }; 139 140 static struct clk pxa27x_clks[] = { 141 INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), 142 INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), 143 144 INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 145 INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 146 INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 147 148 INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), 149 INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 150 INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa27x_device_udc.dev), 151 INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), 152 INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), 153 154 INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), 155 INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), 156 INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), 157 158 INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 159 INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 160 INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 161 INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), 162 INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), 163 164 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), 165 INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL), 166 167 /* 168 INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), 169 INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), 170 INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), 171 INIT_CKEN("IMCLK", IM, 0, 0, NULL), 172 INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), 173 */ 174 }; 175 176 #ifdef CONFIG_PM 177 178 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 179 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 180 181 /* 182 * List of global PXA peripheral registers to preserve. 183 * More ones like CP and general purpose register values are preserved 184 * with the stack pointer in sleep.S. 185 */ 186 enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, 187 188 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 189 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 190 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, 191 SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, 192 193 SLEEP_SAVE_PSTR, 194 195 SLEEP_SAVE_CKEN, 196 197 SLEEP_SAVE_MDREFR, 198 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, 199 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, 200 201 SLEEP_SAVE_COUNT 202 }; 203 204 void pxa27x_cpu_pm_save(unsigned long *sleep_save) 205 { 206 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3); 207 208 SAVE(GAFR0_L); SAVE(GAFR0_U); 209 SAVE(GAFR1_L); SAVE(GAFR1_U); 210 SAVE(GAFR2_L); SAVE(GAFR2_U); 211 SAVE(GAFR3_L); SAVE(GAFR3_U); 212 213 SAVE(MDREFR); 214 SAVE(PWER); SAVE(PCFR); SAVE(PRER); 215 SAVE(PFER); SAVE(PKWR); 216 217 SAVE(CKEN); 218 SAVE(PSTR); 219 } 220 221 void pxa27x_cpu_pm_restore(unsigned long *sleep_save) 222 { 223 /* ensure not to come back here if it wasn't intended */ 224 PSPR = 0; 225 226 /* restore registers */ 227 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 228 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 229 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 230 RESTORE(GAFR3_L); RESTORE(GAFR3_U); 231 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3); 232 233 RESTORE(MDREFR); 234 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); 235 RESTORE(PFER); RESTORE(PKWR); 236 237 PSSR = PSSR_RDH | PSSR_PH; 238 239 RESTORE(CKEN); 240 241 RESTORE(PSTR); 242 } 243 244 void pxa27x_cpu_pm_enter(suspend_state_t state) 245 { 246 extern void pxa_cpu_standby(void); 247 248 /* ensure voltage-change sequencer not initiated, which hangs */ 249 PCFR &= ~PCFR_FVC; 250 251 /* Clear edge-detect status register. */ 252 PEDR = 0xDF12FE1B; 253 254 /* Clear reset status */ 255 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; 256 257 switch (state) { 258 case PM_SUSPEND_STANDBY: 259 pxa_cpu_standby(); 260 break; 261 case PM_SUSPEND_MEM: 262 /* set resume return address */ 263 PSPR = virt_to_phys(pxa_cpu_resume); 264 pxa27x_cpu_suspend(PWRMODE_SLEEP); 265 break; 266 } 267 } 268 269 static int pxa27x_cpu_pm_valid(suspend_state_t state) 270 { 271 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 272 } 273 274 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { 275 .save_count = SLEEP_SAVE_COUNT, 276 .save = pxa27x_cpu_pm_save, 277 .restore = pxa27x_cpu_pm_restore, 278 .valid = pxa27x_cpu_pm_valid, 279 .enter = pxa27x_cpu_pm_enter, 280 }; 281 282 static void __init pxa27x_init_pm(void) 283 { 284 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; 285 } 286 #else 287 static inline void pxa27x_init_pm(void) {} 288 #endif 289 290 /* PXA27x: Various gpios can issue wakeup events. This logic only 291 * handles the simple cases, not the WEMUX2 and WEMUX3 options 292 */ 293 static int pxa27x_set_wake(unsigned int irq, unsigned int on) 294 { 295 int gpio = IRQ_TO_GPIO(irq); 296 uint32_t mask; 297 298 if (gpio >= 0 && gpio < 128) 299 return gpio_set_wake(gpio, on); 300 301 if (irq == IRQ_KEYPAD) 302 return keypad_set_wake(on); 303 304 switch (irq) { 305 case IRQ_RTCAlrm: 306 mask = PWER_RTC; 307 break; 308 case IRQ_USB: 309 mask = 1u << 26; 310 break; 311 default: 312 return -EINVAL; 313 } 314 315 if (on) 316 PWER |= mask; 317 else 318 PWER &=~mask; 319 320 return 0; 321 } 322 323 void __init pxa27x_init_irq(void) 324 { 325 pxa_init_irq(34, pxa27x_set_wake); 326 pxa_init_gpio(128, pxa27x_set_wake); 327 } 328 329 /* 330 * device registration specific to PXA27x. 331 */ 332 333 static struct resource i2c_power_resources[] = { 334 { 335 .start = 0x40f00180, 336 .end = 0x40f001a3, 337 .flags = IORESOURCE_MEM, 338 }, { 339 .start = IRQ_PWRI2C, 340 .end = IRQ_PWRI2C, 341 .flags = IORESOURCE_IRQ, 342 }, 343 }; 344 345 struct platform_device pxa27x_device_i2c_power = { 346 .name = "pxa2xx-i2c", 347 .id = 1, 348 .resource = i2c_power_resources, 349 .num_resources = ARRAY_SIZE(i2c_power_resources), 350 }; 351 352 void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info) 353 { 354 local_irq_disable(); 355 PCFR |= PCFR_PI2CEN; 356 local_irq_enable(); 357 pxa27x_device_i2c_power.dev.platform_data = info; 358 } 359 360 static struct platform_device *devices[] __initdata = { 361 &pxa27x_device_udc, 362 &pxa_device_ffuart, 363 &pxa_device_btuart, 364 &pxa_device_stuart, 365 &pxa_device_i2s, 366 &pxa_device_rtc, 367 &pxa27x_device_i2c_power, 368 &pxa27x_device_ssp1, 369 &pxa27x_device_ssp2, 370 &pxa27x_device_ssp3, 371 &pxa27x_device_pwm0, 372 &pxa27x_device_pwm1, 373 }; 374 375 static struct sys_device pxa27x_sysdev[] = { 376 { 377 .cls = &pxa_irq_sysclass, 378 }, { 379 .cls = &pxa_gpio_sysclass, 380 }, 381 }; 382 383 static int __init pxa27x_init(void) 384 { 385 int i, ret = 0; 386 387 if (cpu_is_pxa27x()) { 388 389 reset_status = RCSR; 390 391 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); 392 393 if ((ret = pxa_init_dma(32))) 394 return ret; 395 396 pxa27x_init_pm(); 397 398 for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) { 399 ret = sysdev_register(&pxa27x_sysdev[i]); 400 if (ret) 401 pr_err("failed to register sysdev[%d]\n", i); 402 } 403 404 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 405 } 406 407 return ret; 408 } 409 410 postcore_initcall(pxa27x_init); 411