1 /* 2 * linux/arch/arm/mach-pxa/pxa27x.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Nov 05, 2002 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code specific to PXA27x aka Bulverde. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/pm.h> 18 #include <linux/platform_device.h> 19 20 #include <asm/hardware.h> 21 #include <asm/irq.h> 22 #include <asm/arch/irqs.h> 23 #include <asm/arch/pxa-regs.h> 24 #include <asm/arch/ohci.h> 25 #include <asm/arch/pm.h> 26 #include <asm/arch/dma.h> 27 28 #include "generic.h" 29 #include "devices.h" 30 31 /* Crystal clock: 13MHz */ 32 #define BASE_CLK 13000000 33 34 /* 35 * Get the clock frequency as reflected by CCSR and the turbo flag. 36 * We assume these values have been applied via a fcs. 37 * If info is not 0 we also display the current settings. 38 */ 39 unsigned int get_clk_frequency_khz( int info) 40 { 41 unsigned long ccsr, clkcfg; 42 unsigned int l, L, m, M, n2, N, S; 43 int cccr_a, t, ht, b; 44 45 ccsr = CCSR; 46 cccr_a = CCCR & (1 << 25); 47 48 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ 49 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); 50 t = clkcfg & (1 << 0); 51 ht = clkcfg & (1 << 2); 52 b = clkcfg & (1 << 3); 53 54 l = ccsr & 0x1f; 55 n2 = (ccsr>>7) & 0xf; 56 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; 57 58 L = l * BASE_CLK; 59 N = (L * n2) / 2; 60 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); 61 S = (b) ? L : (L/2); 62 63 if (info) { 64 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", 65 L / 1000000, (L % 1000000) / 10000, l ); 66 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", 67 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5, 68 (t) ? "" : "in" ); 69 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n", 70 M / 1000000, (M % 1000000) / 10000, m ); 71 printk( KERN_INFO "System bus clock: %d.%02dMHz \n", 72 S / 1000000, (S % 1000000) / 10000 ); 73 } 74 75 return (t) ? (N/1000) : (L/1000); 76 } 77 78 /* 79 * Return the current mem clock frequency in units of 10kHz as 80 * reflected by CCCR[A], B, and L 81 */ 82 unsigned int get_memclk_frequency_10khz(void) 83 { 84 unsigned long ccsr, clkcfg; 85 unsigned int l, L, m, M; 86 int cccr_a, b; 87 88 ccsr = CCSR; 89 cccr_a = CCCR & (1 << 25); 90 91 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ 92 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); 93 b = clkcfg & (1 << 3); 94 95 l = ccsr & 0x1f; 96 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; 97 98 L = l * BASE_CLK; 99 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); 100 101 return (M / 10000); 102 } 103 104 /* 105 * Return the current LCD clock frequency in units of 10kHz as 106 */ 107 unsigned int get_lcdclk_frequency_10khz(void) 108 { 109 unsigned long ccsr; 110 unsigned int l, L, k, K; 111 112 ccsr = CCSR; 113 114 l = ccsr & 0x1f; 115 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; 116 117 L = l * BASE_CLK; 118 K = L / k; 119 120 return (K / 10000); 121 } 122 123 EXPORT_SYMBOL(get_clk_frequency_khz); 124 EXPORT_SYMBOL(get_memclk_frequency_10khz); 125 EXPORT_SYMBOL(get_lcdclk_frequency_10khz); 126 127 #ifdef CONFIG_PM 128 129 void pxa_cpu_pm_enter(suspend_state_t state) 130 { 131 extern void pxa_cpu_standby(void); 132 extern void pxa_cpu_suspend(unsigned int); 133 extern void pxa_cpu_resume(void); 134 135 if (state == PM_SUSPEND_STANDBY) 136 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | (1 << CKEN_LCD) | (1 << CKEN_PWM0); 137 else 138 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER); 139 140 /* ensure voltage-change sequencer not initiated, which hangs */ 141 PCFR &= ~PCFR_FVC; 142 143 /* Clear edge-detect status register. */ 144 PEDR = 0xDF12FE1B; 145 146 switch (state) { 147 case PM_SUSPEND_STANDBY: 148 pxa_cpu_standby(); 149 break; 150 case PM_SUSPEND_MEM: 151 /* set resume return address */ 152 PSPR = virt_to_phys(pxa_cpu_resume); 153 pxa_cpu_suspend(PWRMODE_SLEEP); 154 break; 155 } 156 } 157 158 static int pxa27x_pm_valid(suspend_state_t state) 159 { 160 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 161 } 162 163 static struct pm_ops pxa27x_pm_ops = { 164 .enter = pxa_pm_enter, 165 .valid = pxa27x_pm_valid, 166 }; 167 #endif 168 169 /* 170 * device registration specific to PXA27x. 171 */ 172 173 static u64 pxa27x_dmamask = 0xffffffffUL; 174 175 static struct resource pxa27x_ohci_resources[] = { 176 [0] = { 177 .start = 0x4C000000, 178 .end = 0x4C00ff6f, 179 .flags = IORESOURCE_MEM, 180 }, 181 [1] = { 182 .start = IRQ_USBH1, 183 .end = IRQ_USBH1, 184 .flags = IORESOURCE_IRQ, 185 }, 186 }; 187 188 static struct platform_device pxa27x_device_ohci = { 189 .name = "pxa27x-ohci", 190 .id = -1, 191 .dev = { 192 .dma_mask = &pxa27x_dmamask, 193 .coherent_dma_mask = 0xffffffff, 194 }, 195 .num_resources = ARRAY_SIZE(pxa27x_ohci_resources), 196 .resource = pxa27x_ohci_resources, 197 }; 198 199 void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) 200 { 201 pxa27x_device_ohci.dev.platform_data = info; 202 } 203 204 static struct resource i2c_power_resources[] = { 205 { 206 .start = 0x40f00180, 207 .end = 0x40f001a3, 208 .flags = IORESOURCE_MEM, 209 }, { 210 .start = IRQ_PWRI2C, 211 .end = IRQ_PWRI2C, 212 .flags = IORESOURCE_IRQ, 213 }, 214 }; 215 216 static struct platform_device pxa27x_device_i2c_power = { 217 .name = "pxa2xx-i2c", 218 .id = 1, 219 .resource = i2c_power_resources, 220 .num_resources = ARRAY_SIZE(i2c_power_resources), 221 }; 222 223 static struct platform_device *devices[] __initdata = { 224 &pxa_device_mci, 225 &pxa_device_udc, 226 &pxa_device_fb, 227 &pxa_device_ffuart, 228 &pxa_device_btuart, 229 &pxa_device_stuart, 230 &pxa_device_i2c, 231 &pxa_device_i2s, 232 &pxa_device_ficp, 233 &pxa_device_rtc, 234 &pxa27x_device_i2c_power, 235 &pxa27x_device_ohci, 236 }; 237 238 void __init pxa27x_init_irq(void) 239 { 240 pxa_init_irq_low(); 241 pxa_init_irq_high(); 242 pxa_init_irq_gpio(128); 243 } 244 245 static int __init pxa27x_init(void) 246 { 247 int ret = 0; 248 if (cpu_is_pxa27x()) { 249 if ((ret = pxa_init_dma(32))) 250 return ret; 251 #ifdef CONFIG_PM 252 pm_set_ops(&pxa27x_pm_ops); 253 #endif 254 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 255 } 256 return ret; 257 } 258 259 subsys_initcall(pxa27x_init); 260