xref: /linux/arch/arm/mach-pxa/pxa27x.c (revision a3f4c927d379cfaa597bc8ff75dc9d28f8d9200e) 
1 /*
2  *  linux/arch/arm/mach-pxa/pxa27x.c
3  *
4  *  Author:	Nicolas Pitre
5  *  Created:	Nov 05, 2002
6  *  Copyright:	MontaVista Software Inc.
7  *
8  * Code specific to PXA27x aka Bulverde.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/io.h>
21 #include <linux/irq.h>
22 
23 #include <asm/mach/map.h>
24 #include <mach/hardware.h>
25 #include <asm/irq.h>
26 #include <mach/irqs.h>
27 #include <mach/gpio.h>
28 #include <mach/pxa27x.h>
29 #include <mach/reset.h>
30 #include <mach/ohci.h>
31 #include <mach/pm.h>
32 #include <mach/dma.h>
33 #include <mach/smemc.h>
34 
35 #include <plat/i2c.h>
36 
37 #include "generic.h"
38 #include "devices.h"
39 #include "clock.h"
40 
41 void pxa27x_clear_otgph(void)
42 {
43 	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
44 		PSSR |= PSSR_OTGPH;
45 }
46 EXPORT_SYMBOL(pxa27x_clear_otgph);
47 
48 static unsigned long ac97_reset_config[] = {
49 	GPIO113_GPIO,
50 	GPIO113_AC97_nRESET,
51 	GPIO95_GPIO,
52 	GPIO95_AC97_nRESET,
53 };
54 
55 void pxa27x_assert_ac97reset(int reset_gpio, int on)
56 {
57 	if (reset_gpio == 113)
58 		pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
59 				       &ac97_reset_config[1], 1);
60 
61 	if (reset_gpio == 95)
62 		pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
63 				       &ac97_reset_config[3], 1);
64 }
65 EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
66 
67 /* Crystal clock: 13MHz */
68 #define BASE_CLK	13000000
69 
70 /*
71  * Get the clock frequency as reflected by CCSR and the turbo flag.
72  * We assume these values have been applied via a fcs.
73  * If info is not 0 we also display the current settings.
74  */
75 unsigned int pxa27x_get_clk_frequency_khz(int info)
76 {
77 	unsigned long ccsr, clkcfg;
78 	unsigned int l, L, m, M, n2, N, S;
79        	int cccr_a, t, ht, b;
80 
81 	ccsr = CCSR;
82 	cccr_a = CCCR & (1 << 25);
83 
84 	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
85 	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
86 	t  = clkcfg & (1 << 0);
87 	ht = clkcfg & (1 << 2);
88 	b  = clkcfg & (1 << 3);
89 
90 	l  = ccsr & 0x1f;
91 	n2 = (ccsr>>7) & 0xf;
92 	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
93 
94 	L  = l * BASE_CLK;
95 	N  = (L * n2) / 2;
96 	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
97 	S  = (b) ? L : (L/2);
98 
99 	if (info) {
100 		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
101 			L / 1000000, (L % 1000000) / 10000, l );
102 		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
103 			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
104 			(t) ? "" : "in" );
105 		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
106 			M / 1000000, (M % 1000000) / 10000, m );
107 		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
108 			S / 1000000, (S % 1000000) / 10000 );
109 	}
110 
111 	return (t) ? (N/1000) : (L/1000);
112 }
113 
114 /*
115  * Return the current mem clock frequency as reflected by CCCR[A], B, and L
116  */
117 static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
118 {
119 	unsigned long ccsr, clkcfg;
120 	unsigned int l, L, m, M;
121        	int cccr_a, b;
122 
123 	ccsr = CCSR;
124 	cccr_a = CCCR & (1 << 25);
125 
126 	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
127 	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
128 	b = clkcfg & (1 << 3);
129 
130 	l = ccsr & 0x1f;
131 	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
132 
133 	L = l * BASE_CLK;
134 	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
135 
136 	return M;
137 }
138 
139 static const struct clkops clk_pxa27x_mem_ops = {
140 	.enable		= clk_dummy_enable,
141 	.disable	= clk_dummy_disable,
142 	.getrate	= clk_pxa27x_mem_getrate,
143 };
144 
145 /*
146  * Return the current LCD clock frequency in units of 10kHz as
147  */
148 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
149 {
150 	unsigned long ccsr;
151 	unsigned int l, L, k, K;
152 
153 	ccsr = CCSR;
154 
155 	l = ccsr & 0x1f;
156 	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
157 
158 	L = l * BASE_CLK;
159 	K = L / k;
160 
161 	return (K / 10000);
162 }
163 
164 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
165 {
166 	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
167 }
168 
169 static const struct clkops clk_pxa27x_lcd_ops = {
170 	.enable		= clk_pxa2xx_cken_enable,
171 	.disable	= clk_pxa2xx_cken_disable,
172 	.getrate	= clk_pxa27x_lcd_getrate,
173 };
174 
175 static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
176 static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
177 static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
178 static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
179 static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
180 static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
181 static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
182 static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
183 static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
184 static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
185 static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
186 static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
187 static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
188 static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
189 static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
190 static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
191 static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
192 static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
193 static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
194 static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
195 static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
196 static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
197 static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
198 
199 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
200 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
201 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
202 
203 static struct clk_lookup pxa27x_clkregs[] = {
204 	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
205 	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
206 	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
207 	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
208 	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
209 	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
210 	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
211 	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
212 	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
213 	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
214 	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
215 	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
216 	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
217 	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
218 	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
219 	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
220 	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
221 	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
222 	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
223 	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
224 	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
225 	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
226 	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
227 	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
228 	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
229 	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
230 	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
231 };
232 
233 #ifdef CONFIG_PM
234 
235 #define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
236 #define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]
237 
238 /*
239  * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
240  */
241 static unsigned int pwrmode = PWRMODE_SLEEP;
242 
243 int __init pxa27x_set_pwrmode(unsigned int mode)
244 {
245 	switch (mode) {
246 	case PWRMODE_SLEEP:
247 	case PWRMODE_DEEPSLEEP:
248 		pwrmode = mode;
249 		return 0;
250 	}
251 
252 	return -EINVAL;
253 }
254 
255 /*
256  * List of global PXA peripheral registers to preserve.
257  * More ones like CP and general purpose register values are preserved
258  * with the stack pointer in sleep.S.
259  */
260 enum {
261 	SLEEP_SAVE_PSTR,
262 	SLEEP_SAVE_MDREFR,
263 	SLEEP_SAVE_PCFR,
264 	SLEEP_SAVE_COUNT
265 };
266 
267 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
268 {
269 	sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
270 	SAVE(PCFR);
271 
272 	SAVE(PSTR);
273 }
274 
275 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
276 {
277 	__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
278 	RESTORE(PCFR);
279 
280 	PSSR = PSSR_RDH | PSSR_PH;
281 
282 	RESTORE(PSTR);
283 }
284 
285 void pxa27x_cpu_pm_enter(suspend_state_t state)
286 {
287 	extern void pxa_cpu_standby(void);
288 
289 	/* ensure voltage-change sequencer not initiated, which hangs */
290 	PCFR &= ~PCFR_FVC;
291 
292 	/* Clear edge-detect status register. */
293 	PEDR = 0xDF12FE1B;
294 
295 	/* Clear reset status */
296 	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
297 
298 	switch (state) {
299 	case PM_SUSPEND_STANDBY:
300 		pxa_cpu_standby();
301 		break;
302 	case PM_SUSPEND_MEM:
303 		pxa27x_cpu_suspend(pwrmode);
304 		break;
305 	}
306 }
307 
308 static int pxa27x_cpu_pm_valid(suspend_state_t state)
309 {
310 	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
311 }
312 
313 static int pxa27x_cpu_pm_prepare(void)
314 {
315 	/* set resume return address */
316 	PSPR = virt_to_phys(pxa_cpu_resume);
317 	return 0;
318 }
319 
320 static void pxa27x_cpu_pm_finish(void)
321 {
322 	/* ensure not to come back here if it wasn't intended */
323 	PSPR = 0;
324 }
325 
326 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
327 	.save_count	= SLEEP_SAVE_COUNT,
328 	.save		= pxa27x_cpu_pm_save,
329 	.restore	= pxa27x_cpu_pm_restore,
330 	.valid		= pxa27x_cpu_pm_valid,
331 	.enter		= pxa27x_cpu_pm_enter,
332 	.prepare	= pxa27x_cpu_pm_prepare,
333 	.finish		= pxa27x_cpu_pm_finish,
334 };
335 
336 static void __init pxa27x_init_pm(void)
337 {
338 	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
339 }
340 #else
341 static inline void pxa27x_init_pm(void) {}
342 #endif
343 
344 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
345  * handles the simple cases, not the WEMUX2 and WEMUX3 options
346  */
347 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
348 {
349 	int gpio = IRQ_TO_GPIO(d->irq);
350 	uint32_t mask;
351 
352 	if (gpio >= 0 && gpio < 128)
353 		return gpio_set_wake(gpio, on);
354 
355 	if (d->irq == IRQ_KEYPAD)
356 		return keypad_set_wake(on);
357 
358 	switch (d->irq) {
359 	case IRQ_RTCAlrm:
360 		mask = PWER_RTC;
361 		break;
362 	case IRQ_USB:
363 		mask = 1u << 26;
364 		break;
365 	default:
366 		return -EINVAL;
367 	}
368 
369 	if (on)
370 		PWER |= mask;
371 	else
372 		PWER &=~mask;
373 
374 	return 0;
375 }
376 
377 void __init pxa27x_init_irq(void)
378 {
379 	pxa_init_irq(34, pxa27x_set_wake);
380 	pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
381 }
382 
383 static struct map_desc pxa27x_io_desc[] __initdata = {
384 	{	/* Mem Ctl */
385 		.virtual	= SMEMC_VIRT,
386 		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
387 		.length		= 0x00200000,
388 		.type		= MT_DEVICE
389 	}, {	/* IMem ctl */
390 		.virtual	=  0xfe000000,
391 		.pfn		= __phys_to_pfn(0x58000000),
392 		.length		= 0x00100000,
393 		.type		= MT_DEVICE
394 	},
395 };
396 
397 void __init pxa27x_map_io(void)
398 {
399 	pxa_map_io();
400 	iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
401 	pxa27x_get_clk_frequency_khz(1);
402 }
403 
404 /*
405  * device registration specific to PXA27x.
406  */
407 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
408 {
409 	local_irq_disable();
410 	PCFR |= PCFR_PI2CEN;
411 	local_irq_enable();
412 	pxa_register_device(&pxa27x_device_i2c_power, info);
413 }
414 
415 static struct platform_device *devices[] __initdata = {
416 	&pxa27x_device_udc,
417 	&pxa_device_pmu,
418 	&pxa_device_i2s,
419 	&pxa_device_asoc_ssp1,
420 	&pxa_device_asoc_ssp2,
421 	&pxa_device_asoc_ssp3,
422 	&pxa_device_asoc_platform,
423 	&sa1100_device_rtc,
424 	&pxa_device_rtc,
425 	&pxa27x_device_ssp1,
426 	&pxa27x_device_ssp2,
427 	&pxa27x_device_ssp3,
428 	&pxa27x_device_pwm0,
429 	&pxa27x_device_pwm1,
430 };
431 
432 static struct sys_device pxa27x_sysdev[] = {
433 	{
434 		.cls	= &pxa_irq_sysclass,
435 	}, {
436 		.cls	= &pxa2xx_mfp_sysclass,
437 	}, {
438 		.cls	= &pxa_gpio_sysclass,
439 	}, {
440 		.cls	= &pxa2xx_clock_sysclass,
441 	}
442 };
443 
444 static int __init pxa27x_init(void)
445 {
446 	int i, ret = 0;
447 
448 	if (cpu_is_pxa27x()) {
449 
450 		reset_status = RCSR;
451 
452 		clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
453 
454 		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
455 			return ret;
456 
457 		pxa27x_init_pm();
458 
459 		for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
460 			ret = sysdev_register(&pxa27x_sysdev[i]);
461 			if (ret)
462 				pr_err("failed to register sysdev[%d]\n", i);
463 		}
464 
465 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
466 	}
467 
468 	return ret;
469 }
470 
471 postcore_initcall(pxa27x_init);
472