1 /* 2 * linux/arch/arm/mach-pxa/pxa25x.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Jun 15, 2001 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code specific to PXA21x/25x/26x variants. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Since this file should be linked before any other machine specific file, 15 * the __initcall() here will be executed first. This serves as default 16 * initialization stuff for PXA machines which can be overridden later if 17 * need be. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm.h> 24 25 #include <asm/hardware.h> 26 #include <asm/arch/irqs.h> 27 #include <asm/arch/pxa-regs.h> 28 #include <asm/arch/pm.h> 29 #include <asm/arch/dma.h> 30 31 #include "generic.h" 32 #include "devices.h" 33 #include "clock.h" 34 35 /* 36 * Various clock factors driven by the CCCR register. 37 */ 38 39 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 40 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; 41 42 /* Memory Frequency to Run Mode Frequency Multiplier (M) */ 43 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; 44 45 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ 46 /* Note: we store the value N * 2 here. */ 47 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; 48 49 /* Crystal clock */ 50 #define BASE_CLK 3686400 51 52 /* 53 * Get the clock frequency as reflected by CCCR and the turbo flag. 54 * We assume these values have been applied via a fcs. 55 * If info is not 0 we also display the current settings. 56 */ 57 unsigned int pxa25x_get_clk_frequency_khz(int info) 58 { 59 unsigned long cccr, turbo; 60 unsigned int l, L, m, M, n2, N; 61 62 cccr = CCCR; 63 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); 64 65 l = L_clk_mult[(cccr >> 0) & 0x1f]; 66 m = M_clk_mult[(cccr >> 5) & 0x03]; 67 n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 68 69 L = l * BASE_CLK; 70 M = m * L; 71 N = n2 * M / 2; 72 73 if(info) 74 { 75 L += 5000; 76 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", 77 L / 1000000, (L % 1000000) / 10000, l ); 78 M += 5000; 79 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", 80 M / 1000000, (M % 1000000) / 10000, m ); 81 N += 5000; 82 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", 83 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, 84 (turbo & 1) ? "" : "in" ); 85 } 86 87 return (turbo & 1) ? (N/1000) : (M/1000); 88 } 89 90 /* 91 * Return the current memory clock frequency in units of 10kHz 92 */ 93 unsigned int pxa25x_get_memclk_frequency_10khz(void) 94 { 95 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; 96 } 97 98 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) 99 { 100 return pxa25x_get_memclk_frequency_10khz() * 10000; 101 } 102 103 static const struct clkops clk_pxa25x_lcd_ops = { 104 .enable = clk_cken_enable, 105 .disable = clk_cken_disable, 106 .getrate = clk_pxa25x_lcd_getrate, 107 }; 108 109 /* 110 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) 111 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz 112 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) 113 */ 114 static struct clk pxa25x_clks[] = { 115 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), 116 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), 117 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), 118 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), 119 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), 120 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), 121 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), 122 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), 123 /* 124 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), 125 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), 126 INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL), 127 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), 128 INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL), 129 */ 130 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), 131 }; 132 133 #ifdef CONFIG_PM 134 135 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 136 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 137 138 #define RESTORE_GPLEVEL(n) do { \ 139 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ 140 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ 141 } while (0) 142 143 /* 144 * List of global PXA peripheral registers to preserve. 145 * More ones like CP and general purpose register values are preserved 146 * with the stack pointer in sleep.S. 147 */ 148 enum { SLEEP_SAVE_START = 0, 149 150 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, 151 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, 152 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, 153 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, 154 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, 155 156 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 157 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 158 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, 159 160 SLEEP_SAVE_PSTR, 161 162 SLEEP_SAVE_ICMR, 163 SLEEP_SAVE_CKEN, 164 165 SLEEP_SAVE_SIZE 166 }; 167 168 169 static void pxa25x_cpu_pm_save(unsigned long *sleep_save) 170 { 171 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); 172 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); 173 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); 174 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); 175 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); 176 177 SAVE(GAFR0_L); SAVE(GAFR0_U); 178 SAVE(GAFR1_L); SAVE(GAFR1_U); 179 SAVE(GAFR2_L); SAVE(GAFR2_U); 180 181 SAVE(ICMR); 182 SAVE(CKEN); 183 SAVE(PSTR); 184 } 185 186 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) 187 { 188 /* restore registers */ 189 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); 190 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); 191 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 192 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 193 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 194 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); 195 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); 196 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); 197 198 RESTORE(CKEN); 199 RESTORE(ICMR); 200 RESTORE(PSTR); 201 } 202 203 static void pxa25x_cpu_pm_enter(suspend_state_t state) 204 { 205 CKEN = 0; 206 207 switch (state) { 208 case PM_SUSPEND_MEM: 209 /* set resume return address */ 210 PSPR = virt_to_phys(pxa_cpu_resume); 211 pxa25x_cpu_suspend(PWRMODE_SLEEP); 212 break; 213 } 214 } 215 216 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { 217 .save_size = SLEEP_SAVE_SIZE, 218 .valid = pm_valid_only_mem, 219 .save = pxa25x_cpu_pm_save, 220 .restore = pxa25x_cpu_pm_restore, 221 .enter = pxa25x_cpu_pm_enter, 222 }; 223 224 static void __init pxa25x_init_pm(void) 225 { 226 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; 227 } 228 #endif 229 230 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm 231 */ 232 233 static int pxa25x_set_wake(unsigned int irq, unsigned int on) 234 { 235 int gpio = IRQ_TO_GPIO(irq); 236 uint32_t gpio_bit, mask = 0; 237 238 if (gpio >= 0 && gpio <= 15) { 239 gpio_bit = GPIO_bit(gpio); 240 mask = gpio_bit; 241 if (on) { 242 if (GRER(gpio) | gpio_bit) 243 PRER |= gpio_bit; 244 else 245 PRER &= ~gpio_bit; 246 247 if (GFER(gpio) | gpio_bit) 248 PFER |= gpio_bit; 249 else 250 PFER &= ~gpio_bit; 251 } 252 goto set_pwer; 253 } 254 255 if (irq == IRQ_RTCAlrm) { 256 mask = PWER_RTC; 257 goto set_pwer; 258 } 259 260 return -EINVAL; 261 262 set_pwer: 263 if (on) 264 PWER |= mask; 265 else 266 PWER &=~mask; 267 268 return 0; 269 } 270 271 void __init pxa25x_init_irq(void) 272 { 273 pxa_init_irq_low(); 274 pxa_init_irq_gpio(85); 275 pxa_init_irq_set_wake(pxa25x_set_wake); 276 } 277 278 static struct platform_device *pxa25x_devices[] __initdata = { 279 &pxa_device_mci, 280 &pxa_device_udc, 281 &pxa_device_fb, 282 &pxa_device_ffuart, 283 &pxa_device_btuart, 284 &pxa_device_stuart, 285 &pxa_device_i2c, 286 &pxa_device_i2s, 287 &pxa_device_ficp, 288 &pxa_device_rtc, 289 }; 290 291 static int __init pxa25x_init(void) 292 { 293 int ret = 0; 294 295 if (cpu_is_pxa21x() || cpu_is_pxa25x()) { 296 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); 297 298 if ((ret = pxa_init_dma(16))) 299 return ret; 300 #ifdef CONFIG_PM 301 pxa25x_init_pm(); 302 #endif 303 ret = platform_add_devices(pxa25x_devices, 304 ARRAY_SIZE(pxa25x_devices)); 305 } 306 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 307 if (cpu_is_pxa25x()) 308 ret = platform_device_register(&pxa_device_hwuart); 309 310 return ret; 311 } 312 313 subsys_initcall(pxa25x_init); 314