1 /* 2 * linux/arch/arm/mach-pxa/pxa25x.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Jun 15, 2001 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code specific to PXA21x/25x/26x variants. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Since this file should be linked before any other machine specific file, 15 * the __initcall() here will be executed first. This serves as default 16 * initialization stuff for PXA machines which can be overridden later if 17 * need be. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/platform_device.h> 23 #include <linux/suspend.h> 24 #include <linux/sysdev.h> 25 26 #include <asm/hardware.h> 27 #include <asm/arch/irqs.h> 28 #include <asm/arch/pxa-regs.h> 29 #include <asm/arch/pm.h> 30 #include <asm/arch/dma.h> 31 32 #include "generic.h" 33 #include "devices.h" 34 #include "clock.h" 35 36 /* 37 * Various clock factors driven by the CCCR register. 38 */ 39 40 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 41 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; 42 43 /* Memory Frequency to Run Mode Frequency Multiplier (M) */ 44 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; 45 46 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ 47 /* Note: we store the value N * 2 here. */ 48 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; 49 50 /* Crystal clock */ 51 #define BASE_CLK 3686400 52 53 /* 54 * Get the clock frequency as reflected by CCCR and the turbo flag. 55 * We assume these values have been applied via a fcs. 56 * If info is not 0 we also display the current settings. 57 */ 58 unsigned int pxa25x_get_clk_frequency_khz(int info) 59 { 60 unsigned long cccr, turbo; 61 unsigned int l, L, m, M, n2, N; 62 63 cccr = CCCR; 64 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); 65 66 l = L_clk_mult[(cccr >> 0) & 0x1f]; 67 m = M_clk_mult[(cccr >> 5) & 0x03]; 68 n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 69 70 L = l * BASE_CLK; 71 M = m * L; 72 N = n2 * M / 2; 73 74 if(info) 75 { 76 L += 5000; 77 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", 78 L / 1000000, (L % 1000000) / 10000, l ); 79 M += 5000; 80 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", 81 M / 1000000, (M % 1000000) / 10000, m ); 82 N += 5000; 83 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", 84 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, 85 (turbo & 1) ? "" : "in" ); 86 } 87 88 return (turbo & 1) ? (N/1000) : (M/1000); 89 } 90 91 /* 92 * Return the current memory clock frequency in units of 10kHz 93 */ 94 unsigned int pxa25x_get_memclk_frequency_10khz(void) 95 { 96 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; 97 } 98 99 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) 100 { 101 return pxa25x_get_memclk_frequency_10khz() * 10000; 102 } 103 104 static const struct clkops clk_pxa25x_lcd_ops = { 105 .enable = clk_cken_enable, 106 .disable = clk_cken_disable, 107 .getrate = clk_pxa25x_lcd_getrate, 108 }; 109 110 /* 111 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) 112 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz 113 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) 114 */ 115 static struct clk pxa25x_hwuart_clk = 116 INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) 117 ; 118 119 static struct clk pxa25x_clks[] = { 120 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), 121 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), 122 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), 123 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), 124 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), 125 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), 126 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), 127 128 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), 129 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), 130 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), 131 132 /* 133 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), 134 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), 135 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), 136 */ 137 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), 138 }; 139 140 #ifdef CONFIG_PM 141 142 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 143 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 144 145 #define RESTORE_GPLEVEL(n) do { \ 146 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ 147 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ 148 } while (0) 149 150 /* 151 * List of global PXA peripheral registers to preserve. 152 * More ones like CP and general purpose register values are preserved 153 * with the stack pointer in sleep.S. 154 */ 155 enum { SLEEP_SAVE_START = 0, 156 157 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, 158 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, 159 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, 160 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, 161 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, 162 163 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 164 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 165 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, 166 167 SLEEP_SAVE_PSTR, 168 169 SLEEP_SAVE_CKEN, 170 171 SLEEP_SAVE_SIZE 172 }; 173 174 175 static void pxa25x_cpu_pm_save(unsigned long *sleep_save) 176 { 177 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); 178 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); 179 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); 180 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); 181 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); 182 183 SAVE(GAFR0_L); SAVE(GAFR0_U); 184 SAVE(GAFR1_L); SAVE(GAFR1_U); 185 SAVE(GAFR2_L); SAVE(GAFR2_U); 186 187 SAVE(CKEN); 188 SAVE(PSTR); 189 190 /* Clear GPIO transition detect bits */ 191 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; 192 } 193 194 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) 195 { 196 /* ensure not to come back here if it wasn't intended */ 197 PSPR = 0; 198 199 /* restore registers */ 200 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); 201 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); 202 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 203 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 204 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 205 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); 206 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); 207 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); 208 209 PSSR = PSSR_RDH | PSSR_PH; 210 211 RESTORE(CKEN); 212 RESTORE(PSTR); 213 } 214 215 static void pxa25x_cpu_pm_enter(suspend_state_t state) 216 { 217 switch (state) { 218 case PM_SUSPEND_MEM: 219 /* set resume return address */ 220 PSPR = virt_to_phys(pxa_cpu_resume); 221 pxa25x_cpu_suspend(PWRMODE_SLEEP); 222 break; 223 } 224 } 225 226 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { 227 .save_size = SLEEP_SAVE_SIZE, 228 .valid = suspend_valid_only_mem, 229 .save = pxa25x_cpu_pm_save, 230 .restore = pxa25x_cpu_pm_restore, 231 .enter = pxa25x_cpu_pm_enter, 232 }; 233 234 static void __init pxa25x_init_pm(void) 235 { 236 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; 237 } 238 #else 239 static inline void pxa25x_init_pm(void) {} 240 #endif 241 242 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm 243 */ 244 245 static int pxa25x_set_wake(unsigned int irq, unsigned int on) 246 { 247 int gpio = IRQ_TO_GPIO(irq); 248 uint32_t gpio_bit, mask = 0; 249 250 if (gpio >= 0 && gpio <= 15) { 251 gpio_bit = GPIO_bit(gpio); 252 mask = gpio_bit; 253 if (on) { 254 if (GRER(gpio) | gpio_bit) 255 PRER |= gpio_bit; 256 else 257 PRER &= ~gpio_bit; 258 259 if (GFER(gpio) | gpio_bit) 260 PFER |= gpio_bit; 261 else 262 PFER &= ~gpio_bit; 263 } 264 goto set_pwer; 265 } 266 267 if (irq == IRQ_RTCAlrm) { 268 mask = PWER_RTC; 269 goto set_pwer; 270 } 271 272 return -EINVAL; 273 274 set_pwer: 275 if (on) 276 PWER |= mask; 277 else 278 PWER &=~mask; 279 280 return 0; 281 } 282 283 void __init pxa25x_init_irq(void) 284 { 285 pxa_init_irq_low(); 286 pxa_init_irq_gpio(85); 287 pxa_init_irq_set_wake(pxa25x_set_wake); 288 } 289 290 static struct platform_device *pxa25x_devices[] __initdata = { 291 &pxa_device_udc, 292 &pxa_device_ffuart, 293 &pxa_device_btuart, 294 &pxa_device_stuart, 295 &pxa_device_i2s, 296 &pxa_device_rtc, 297 &pxa25x_device_ssp, 298 &pxa25x_device_nssp, 299 &pxa25x_device_assp, 300 }; 301 302 static struct sys_device pxa25x_sysdev[] = { 303 { 304 .cls = &pxa_irq_sysclass, 305 }, 306 }; 307 308 static int __init pxa25x_init(void) 309 { 310 int i, ret = 0; 311 312 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 313 if (cpu_is_pxa25x()) 314 clks_register(&pxa25x_hwuart_clk, 1); 315 316 if (cpu_is_pxa21x() || cpu_is_pxa25x()) { 317 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); 318 319 if ((ret = pxa_init_dma(16))) 320 return ret; 321 322 pxa25x_init_pm(); 323 324 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { 325 ret = sysdev_register(&pxa25x_sysdev[i]); 326 if (ret) 327 pr_err("failed to register sysdev[%d]\n", i); 328 } 329 330 ret = platform_add_devices(pxa25x_devices, 331 ARRAY_SIZE(pxa25x_devices)); 332 if (ret) 333 return ret; 334 } 335 336 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 337 if (cpu_is_pxa25x()) 338 ret = platform_device_register(&pxa_device_hwuart); 339 340 return ret; 341 } 342 343 subsys_initcall(pxa25x_init); 344